AD7656BSTZ-1 Analog Devices Inc, AD7656BSTZ-1 Datasheet - Page 24

• Manufacturer Part Number: AD7656BSTZ-1
• Description: 6-CHANNEL 16-BIT SE BIPOLAR I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD7656BSTZ-1

• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Data Interface: Serial, Parallel
• Number Of Converters: 6
• Power Dissipation (max): 143mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7656-1EDZ - BOARD EVAL CONTROL AD7656-1EVAL-AD7656-1CBZ - BOARD EVAL FOR AD7656-1EVAL-AD7656CBZ - BOARD EVAL FOR AD7656
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7656-1/AD7657-1/AD7658-1
SOFTWARE SELECTION OF ADCS
The H /S SEL pin determines the source of the combination of ADCs
that are to be simultaneously sampled. When the H /S SEL pin
is logic low, the combination of channels to be simultaneously
sampled is determined by the CONVST A, CONVST B, and
CONVST C pins. When the H /S SEL pin is logic high, the
combination of channels selected for simultaneous sampling
is determined by the contents of the DB15 to DB13 control
registers. In this mode, a write to the control register is necessary.
The control register is an 8-bit write-only register. Data is written
to this register using the CS and WR pins and the DB[15:8] data
pins (see
and
set the corresponding data line high during the write operation.
The AD7656-1/AD7657-1/AD7658-1 control register allows
individual ranges to be programmed on each ADC pair. DB12
to DB10 in the control register are used to program the range
on each ADC pair.
After a reset occurs on the AD7656-1/AD7657-1/AD7658-1,
the control register contains all 0s.
The CONVST A signal is used to initiate a simultaneous
conversion on the combination of channels selected via the
control register. The CONVST B and CONVST C signals can be
tied low when operating in software mode ( H /S SEL = 1). The
number of read pulses required depends on the number of
ADCs selected in the control register and on whether the
devices are operating in word or byte mode. The conversion
results are output in ascending order.
During the write operation, Data Bus Bit DB15 to Data Bus Bit DB8
are bidirectional and become inputs to the control register when
RD is logic high and CS and WR are logic low. The logic state
on DB15 through DB8 is latched into the control register when
WR goes logic high.
Table 10. Control Register Bit Map
DB15
VC
1
Default all 0s.
DB15 TO DB8
Table 11
Figure 31. Parallel Interface—Write Cycle for Word Mode ( W /B = 0)
DB14
VB
Figure 31
WR
CS
. To select an ADC pair to be simultaneously sampled,
DB13
VA
). The control register is detailed in
t
12
DB12
RNGC
t
11
t
DATA
14
DB11
RNGB
1
t
15
DB10
RNGA
t
13
DB9
REFEN
Table 10
DB8
REFBUF
Rev. C | Page 24 of 32
Table 11. Control Register Bit Function Descriptions
Bit
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
Mnemonic
VC
VB
VA
RNGC
RNGB
RNGA
REFEN
REFBUF
Description
This bit is used to select the V5 and V6
analog inputs for the next conversion.
When this bit is set to 1, V5 and V6 are
simultaneously converted on the next
CONVST A rising edge.
This bit is used to select the V3 and V4
analog inputs for the next conversion.
When this bit is set to 1, V3 and V4 are
simultaneously converted on the next
CONVST A rising edge.
This bit is used to select the V1 and V2
analog inputs for the next conversion.
When this bit is set to 1, V1 and V2 are
simultaneously converted on the next
CONVST A rising edge.
This bit is used to select the analog input
range for the V5 and V6 analog inputs.
When this bit is set to 1, the ±2 × V
is selected for the next conversion. When
this bit is set to 0, the ±4 × V
selected for the next conversion.
This bit is used to select the analog input
range for the V3 and V4 analog inputs.
When this bit is set to 1, the ±2 × V
is selected for the next conversion. When
this bit is set to 0, the ±4 × V
selected for the next conversion.
This bit is used to select the analog input
range for the V1 and V2 analog inputs.
When this bit is set to 1, the ±2 × V
is selected for the next conversion. When
this bit is set to 0, the ±4 × V
selected for the next conversion.
This bit is used to select the internal
reference or an external reference. When
this bit is set to 0, the external reference
mode is selected. When this bit is set to 1,
the internal reference is selected.
This bit is used to select between using the
internal reference buffers and choosing
to bypass these reference buffers. When
this bit is set to 0, the internal reference
buffers are enabled and decoupling is
required on the REFCAPx pins. When this
bit is set to 1, the internal reference buffers
are disabled and a buffered reference
should be applied to the REFCAPx pins.
REF
REF
REF
range is
range is
range is
REF
REF
REF
range
range
range