AD7476SRTZ-R2 Analog Devices Inc, AD7476SRTZ-R2 Datasheet - Page 18

• Manufacturer Part Number: AD7476SRTZ-R2
• Description: IC,A/D CONVERTER,SINGLE,12-BIT,TSOP,6PIN
• Manufacturer: Analog Devices Inc

Specifications of AD7476SRTZ-R2

• Design Resources: Output Channel Monitoring Using AD5380 (CN0008) AD5382 Channel Monitor Function (CN0012) AD5381 Channel Monitor Function (CN0013) AD5383 Channel Monitor Function (CN0015) AD5390/91/92 Channel Monitor Function (CN0030) Power off protected data acquisition signal chain using ADG4612 , AD711, and AD7476 (CN0165)
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 17.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7476ACBZ - BOARD EVALUATION FOR AD7476AAD7476-DBRD - BOARD EVAL FOR AD7476AD7476A-DBRD - BOARD EVAL FOR AD7476A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7476/AD7477/AD7478
SERIAL INTERFACE
Figure 23, Figure 24, and Figure 25 show the detailed timing
diagrams for serial interfacing to the AD7476, AD7477, and
AD7478, respectively. The serial clock provides the conversion
clock and controls the transfer of information from the part
during conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode,
takes the bus out of three-state, and samples the analog input at
this point. The conversion initiates and requires 16 SCLK cycles
to complete. Once 13 SCLK falling edges have elapsed, the
track-and-hold goes back into track on the next SCLK rising
edge as shown at Point B in Figure 23, Figure 24, and Figure 25.
On the sixteenth SCLK falling edge, the SDATA line will go
back into three-state. If the rising edge of CS occurs before
16 SCLKs have elapsed, the conversion terminates and the
SDATA line goes back into three-state; otherwise, SDATA
returns to three-state on the 16th SCLK falling edge as shown in
Figure 23, Figure 24, and Figure 25.
SDATA
SDATA
SDATA
SCLK
SCLK
SCLK
CS
CS
CS
THREE-
THREE-
THREE-
STATE
STATE
STATE
t
t
t
2
2
2
Z
Z
Z
t
1
t
t
1
1
3
3
3
ZERO
ZERO
ZERO
4 LEADING ZEROS
4 LEADING ZEROS
4 LEADING ZEROS
2
2
2
ZERO
ZERO
ZERO
3
3
3
ZERO
ZERO
ZERO
Figure 23. AD7476 Serial Interface Timing Diagram
Figure 24. AD7477 Serial Interface Timing Diagram
Figure 25. AD7478 Serial Interface Timing Diagram
4
4
4
DB11
DB9
DB7
t
t
t
4
4
4
t
t
t
6
6
6
8 BITS OF DATA
t
t
t
CONVERT
CONVERT
CONVERT
5
5
DB10
DB8
Rev. E | Page 18 of 24
12
t
t
t
ZERO
7
7
7
13
13
13
4 TRAILING ZEROS
ZERO
DB2
DB0
B
B
B
Sixteen serial clock cycles are required to perform the
conversion process and to access data from the AD7476/
AD7477/AD7478.
CS going low provides the first leading zero to be read by the
microcontroller or DSP. The remaining data is then clocked out
by subsequent SCLK falling edges, beginning with the second
leading zero. Thus, the first falling clock edge on the serial clock
has the first leading zero provided and also clocks out the
second leading zero. The final bit in the data transfer is valid on
the 16th falling edge, having clocked out on the previous (15th)
falling edge. In applications with a slower SCLK, it is possible to
read data on each SCLK rising edge, although the first leading
zero has to be read on the first SCLK falling edge after the CS
falling edge. Therefore, the first rising edge of SCLK after the
CS falling edge provides the second leading zero. The 15th
rising SCLK edge has DB0 provided or the final zero for the
AD7477 and AD7478. This may not work with most
microcontrollers/DSPs, but could possibly be used with FPGAs
and ASICs.
14
14
14
t
t
t
5
5
5
2 TRAILING ZEROS
ZERO
ZERO
DB1
15
15
15
ZERO
ZERO
t
t
DB0
t
8
8
8
16
16
16
THREE-STATE
THREE-STATE
THREE-STATE
t
t
t
QUIET
QUIET
QUIET
t
t
t
1
1
1