AD7394ARZ Analog Devices Inc, AD7394ARZ Datasheet - Page 13

• Manufacturer Part Number: AD7394ARZ
• Description: X2, 12-Bit, +3V UPwr DAC
• Manufacturer: Analog Devices Inc

Specifications of AD7394ARZ

• Settling Time: 60µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 1mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Number Of Channels: 2
• Resolution: 12b
• Conversion Rate: 17KSPS
• Interface Type: Serial (3-Wire)
• Single Supply Voltage (typ): 3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: R-2R
• Power Supply Requirement: Single
• Output Type: Voltage
• Integral Nonlinearity Error: ±2LSB
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 14
• Package Type: SOIC N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

POWER SUPPLY
The very low power consumption of the AD7394 is a direct
result of a circuit design optimizing the use of a CBCMOS process.
By using the low power characteristics of CMOS for the logic,
and the low noise, tight matching of the complementary bipolar
transistors, excellent analog accuracy is achieved. One advan-
tage of the rail-to-rail output amplifiers used in the AD7394 is
the wide range of usable supply voltage. The part is fully
specified and tested for operation from 2.7 V to 5.5 V.
POWER SUPPLY BYPASSING AND GROUNDING
Local supply bypassing consisting of a 10 μF tantalum
electrolytic in parallel with a 0.1 μF ceramic capacitor is
recommended in all applications (Figure 20).
*OPTIONAL EXTERNAL
REFERENCE BYPASS
LDA, LDB
Figure 20. Recommended Supply Bypassing for the AD7394
CLK
SDI
CS
RS
*
C
REFV
DGND
AD7394
2.7V TO 5.5V
DD
AGND
0.1µF
10µF
V
V
OUTA
OUTB
Rev. A | Page 13 of 16
INPUT LOGIC LEVELS
All digital inputs are protected with a Zener-type ESD protection
structure (Figure 21) that allows logic input voltages to exceed
the V
driving one or more of the digital inputs with a 5 V CMOS logic
input-voltage level while operating the AD7394 on a 3 V power
supply. If this mode of interface is used, make sure that the V
of the 5 V CMOS meets the V
AD7394 operating at 3 V. See Figure 12 for a graph of digital
logic input threshold vs. operating V
To minimize power dissipation from input logic levels that are
near the V
trigger design was used that minimizes the input buffer current
consumption compared to traditional CMOS input stages.
Figure 11 is a plot of incremental input voltage vs. supply current
showing that negligible current consumption takes place when
logic levels are in their quiescent state. The normal crossover
current still occurs during logic transitions. A secondary
advantage of this Schmitt trigger is the prevention of false
triggers that would occur with slow moving logic transitions
when a standard CMOS logic interface or opto isolators are
used. The logic inputs SDI, CLK, CS , LDA , LDB , RS , and
SHDN all contain the Schmitt trigger circuits.
DD
supply voltage. This feature can be useful if the user is
IH
Figure 21. Equivalent Digital Input ESD Protection
and V
LOGIC
GND
V
DD
IN
IL
logic input voltage specifications, a Schmitt
IL
input requirement of the
DD
supply voltage.
AD7394
OL