AD7357YRUZ-RL Analog Devices Inc, AD7357YRUZ-RL Datasheet - Page 16

• Manufacturer Part Number: AD7357YRUZ-RL
• Description: 14-Bit Dual Diff Simult 5 MSPS ADC I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD7357YRUZ-RL

• Design Resources: DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7357 (CN0061)
• Number Of Bits: 14
• Sampling Rate (per Second): 4.2M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 59mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7357
FULL POWER-DOWN MODE
This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required, as power-up from a full power-down takes substantially
longer than that from a partial power-down. This mode is more
suited to applications where a series of conversions performed
at a relatively high throughput rate are followed by a long period
of inactivity and, thus, power-down. When the AD7357 is in
full power-down, all analog circuitry is powered down. Full
power-down is entered in a way that is similar to partial power-
down, except that the timing sequence shown in Figure 25 must
be executed twice. The conversion process must be interrupted
in a similar fashion by bringing CS high anywhere after the
second falling edge of SCLK and before the 10
SCLK. The device enters partial power-down mode at this
point.
SDATA
SDATA
SDATA
SDATA
SDATA
SDATA
SCLK
SCLK
SCLK
CS
CS
CS
A
B
B
A
A
B
THE PART BEGINS
TO POWER UP.
1
1
1
2
INVALID DATA
THE PART BEGINS
TO POWER UP.
PARTIAL POWER DOWN.
THE PART ENTERS
INVALID DATA
INVALID DATA
th
falling edge of
t
POWER-UP1
t
POWER-UP2
Figure 26. Exiting Partial Power-Down Mode
Figure 27. Entering Full Power-Down Mode
10
Figure 28. Exiting Full Power-Down Mode
10
THREE-STATE
10
Rev. A | Page 16 of 20
14
14
THE P
14
TO POWER UP.
ART BEGINS
To reach full power-down, the next conversion cycle must be
interrupted in the same way, as shown in Figure 27. When CS
has been brought high in this window of SCLKs, the part
completely powers down.
Note that it is not necessary to complete the 16 SCLKs once CS
has been brought high to enter a power-down mode.
To exit full power-down mode and power up the AD7357, perform
a dummy conversion, such as powering up from partial power-
down. On the falling edge of CS , the device begins to power up,
as long as CS is held low until after the falling edge of the 10
SCLK. The required power-up time must elapse before a con-
version can be initiated, as shown in
1
2
INVALID DATA
1
1
THE PART IS FULLY
POWERED UP; SEE THE
POWER-UP TIMES
SECTION.
THE PART IS FULLY POWERED UP,
SEE POWER-UP TIMES SECTION.
FULL POWER DOWN.
THE PART ENTERS
VALID DATA
VALID DATA
10
THREE-STATE
14
14
Figure 28
14
.
th