AD7352YRUZ-RL Analog Devices Inc, AD7352YRUZ-RL Datasheet - Page 5

• Manufacturer Part Number: AD7352YRUZ-RL
• Description: 12-Bit Dual Diff Simult 3 MSPS ADC I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD7352YRUZ-RL

• Design Resources: DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7352 (CN0040)
• Number Of Bits: 12
• Sampling Rate (per Second): 3M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 45mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING SPECIFICATIONS
V
Table 3.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
1
2
3
SCLK
4
CONVERT
QUIET
2
3
5
6
7
8
9
10
Temperature ranges are as follows: Y grade: −40°C to +125°C; B grade: −40°C to +85°C.
Specified with a load capacitance of 10 pF on SDATA
The time required for the output to cross 0.4 V or 2.4 V.
2,
2
2
2
DD
2
3
= 2.5 V ± 10%, V
Limit at T
50
48
t
5
5
6
12.5
11
9.5
9
5
5
3.5
9.5
5
4.5
9.5
2
+ 13 × t
DRIVE
SCLK
MIN
= 2.25 V to 3.6 V, internal reference = 2.048 V, T
, T
MAX
Unit
kHz min
MHz max
ns max
ns min
ns min
ns max
ns max
ns max
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns max
A
and SDATA
B
.
Description
t
Minimum time between end of serial read and next falling edge of CS
CS to SCLK setup time
Delay from CS until SDATA
Data access time after SCLK falling edge
1.8 V ≤ V
2.25 V ≤ V
2.75 V ≤ V
3.3 V ≤ V
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
CS rising edge to SDATA , SDATA
CS rising edge to falling edge pulse width
SCLK falling edge to SDATA
SCLK falling edge to SDATA
SCLK
Rev. 0 | Page 5 of 20
= 1/f
DRIVE
DRIVE
SCLK
DRIVE
DRIVE
< 2.25 V
≤ 3.6 V
< 2.75 V
< 3.3 V
A
= T
MAX
A
to T
A
A
A
and SDATA
, SDATA
, SDATA
MIN
B
1
high impedance
, unless otherwise noted.
B
B
high impedance
high impedance
B
are three-state disabled
AD7352