AD73360ASUZ-REEL Analog Devices Inc, AD73360ASUZ-REEL Datasheet - Page 15
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AD73360ASUZ-REEL
Manufacturer Part Number
AD73360ASUZ-REEL
Description
6-CHANNEL SIGMA-DELTA ADC I.C.
Manufacturer
Analog Devices Inc
Datasheet
1.AD73360LARZ-REEL.pdf
(35 pages)
Specifications of AD73360ASUZ-REEL
Number Of Bits
16
Number Of Channels
6
Power (watts)
80mW
Voltage - Supply, Analog
2.7 V ~ 3.3 V
Voltage - Supply, Digital
2.7 V ~ 3.3 V
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-AD73360LEB - BOARD EVAL FOR AD73360L
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD73360ASUZ-REEL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
REV. A
CONTROL REGISTER A
CONTROL REGISTER B
CONTROL REGISTER C
Bit Name
0
1
2
3
4
5
6
7
Bit Name
0
1
2
3
4
5
6
7
Bit Name
0
1
2
3
4
5
6
7
RESET
5VEN
C E E
7
7
7
DATA/PGM
MM
Reserved
SLB
DC0
DC1
DC2
RESET
DR0
DR1
SCD0
SCD1
MCD0
MCD1
MCD2
CEE
GPU
Reserved
Reserved
Reserved
Reserved
PUREF
RU
5VEN
Table VIII. Control Register B Description
Table VII. Control Register A Description
Table IX. Control Register C Description
MCD2
DC2
RU
6
6
6
Description
Operating Mode (0 = Program; 1 = Data Mode)
Mixed Mode (0 = OFF; 1 = Enabled)
Must Be Programmed to Zero (0)
SPORT Loop-Back Mode (0 = OFF; 1 = Enabled)
Device Count (Bit 0)
Device Count (Bit 1)
Device Count (Bit 2)
Software Reset (0 = OFF; 1 = Initiates Reset)
Description
Decimation Rate (Bit 0)
Decimation Rate (Bit 1)
Serial Clock Divider (Bit 0)
Serial Clock Divider (Bit 1)
Master Clock Divider (Bit 0)
Master Clock Divider (Bit 1)
Master Clock Divider (Bit 2)
Control Echo Enable (0 = OFF; 1 = Enabled)
Description
Global Power-Up Device (0 = Power Down; 1 = Power Up)
Must Be Programmed to Zero (0)
Must Be Programmed to Zero (0)
Must Be Programmed to Zero (0)
Must Be Programmed to Zero (0)
REF Power (0 = Power Down; 1 = Power Up)
REFOUT Use (0 = Disable REFOUT; 1 = Enable REFOUT)
Enable 5 V Operating Mode (0 = Disable 5 V Mode;
1 = Enable 5 V Mode)
PUREF
MCD1
DC1
5
5
5
–15–
DC0
MCD0
4
4
4
–
SLB
SCD1
3
3
3
–
2
–
SCD0
2
2
–
MM
1
DR1
1
1
–
DATA/PGM
GPU
0
DR0
0
0
AD73360