AD724JR Analog Devices Inc, AD724JR Datasheet

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AD724JR

Manufacturer Part Number
AD724JR
Description
TV / Video IC
Manufacturer
Analog Devices Inc
Type
Video Encoderr
Datasheet

Specifications of AD724JR

No. Of Pins
16
Peak Reflow Compatible (260 C)
No
Leaded Process Compatible
No
Package / Case
16-SOIC
Rohs Status
RoHS non-compliant
Applications
RGB To NTSC/PAL
Voltage - Supply, Digital
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Voltage - Supply, Analog
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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a
PRODUCT DESCRIPTION
The AD724 is a low cost RGB to NTSC/PAL Encoder that
converts red, green and blue color component signals into their
corresponding luminance (baseband amplitude) and chromi-
nance (subcarrier amplitude and phase) signals in accordance
with either NTSC or PAL standards. These two outputs are also
combined to provide composite video output. All three outputs can
simultaneously drive 75 , reverse-terminated cables. All logi-
cal inputs are TTL, 3 V and 5 V CMOS compatible. The chip
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FEATURES
Low Cost, Integrated Solution
+5 V Operation
Accepts FSC Clock or Crystal, or 4FSC Clock
Composite Video and Separate Y/C (S-Video) Outputs
Luma and Chroma Outputs Are Time Aligned
Minimal External Components:
Phase Lock to External Subcarrier
Drives 75
Logic Selectable NTSC or PAL Encoding Modes
Compact 16-Lead SOIC
APPLICATIONS
RGB to NTSC or PAL Encoding
NTSC/PAL
CARRIER
No External Filters or Delay Lines Required
Onboard DC Clamp
Accepts Either HSYNC and VSYNC or CSYNC
GREEN
HSYNC
VSYNC
BLUE
SUB-
RED
4FSC
FSC
Reverse-Terminated Loads
CLAMP
CLAMP
CLAMP
4FSC
4FSC
DC
DC
DC
XNOR
CSYNC
QUADRATURE
RGB-TO-YUV
SEPARATOR
DECODER
ENCODING
MATRIX
XOSC
SYNC
+4
DETECTOR
PHASE
U
Y
V
FSC
FSC 90
FSC 0
LP PRE-
4-POLE
4-POLE
CSYNC
3-POLE
FILTER
FUNCTIONAL BLOCK DIAGRAM
BURST
°
LPF
LPF
CHARGE
°
PUMP
CSYNC
BURST
CLAMP
CLAMP
(PAL ONLY)
NTSC/PAL
U
V
FILTER
LOOP
180
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
operates from a single +5 V supply. No external delay lines or
filters are required. The AD724 may be powered down when
not in use.
The AD724 accepts either FSC or 4FSC clock. When a clock is
not available, a low cost parallel-resonant crystal (3.58 MHz
(NTSC) or 4.43 MHz (PAL)) and the AD724’s on-chip oscilla-
tor generate the necessary subcarrier clock. The AD724 also
accepts the subcarrier clock from an external video source.
The interface to graphics controllers is simple: an on-chip logic
“XNOR” accepts the available vertical (VSYNC) and horizon-
tal sync (HSYNC) signals and creates the composite sync
(CSYNC) signal on-chip. If available, the AD724 will also
accept a standard CSYNC signal by connecting VSYNC to
Logic HI and applying CSYNC to the HSYNC pin. The
AD724 contains decoding logic to identify valid horizontal sync
pulses for correct burst insertion.
Delays in the U and V chroma filters are matched by an on-chip
sampled-data delay line in the Y signal path. To prevent alias-
ing, a prefilter at 5 MHz is included ahead of the delay line and
a post-filter at 5 MHz is added after the delay line to suppress
harmonics in the output. These low-pass filters are optimized
for minimum pulse overshoot. The overall luma delay, relative
to chroma, has been designed to be time aligned for direct input to
a television’s baseband. The AD724 comes in a space-saving
SOIC and is specified for the 0 C to +70 C commercial tem-
perature range.
SC 90
4FSC
VCO
MODULATORS
°
/270
BALANCED
°
DELAY LINE
RGB to NTSC/PAL Encoder
SAMPLED-
AT 8FSC
CLOCK
DATA
World Wide Web Site: http://www.analog.com
NTSC/PAL
LP POST-
4-POLE
2-POLE
FILTER
LPF
© Analog Devices, Inc., 1999
X2
X2
X2
AD724
LUMINANCE
OUTPUT
COMPOSITE
OUTPUT
CHROMINANCE
OUTPUT

Related parts for AD724JR

AD724JR Summary of contents

Page 1

FEATURES Low Cost, Integrated Solution +5 V Operation Accepts FSC Clock or Crystal, or 4FSC Clock Composite Video and Separate Y/C (S-Video) Outputs Luma and Chroma Outputs Are Time Aligned Minimal External Components: No External Filters or Delay Lines ...

Page 2

AD724–SPECIFICATIONS Parameter SIGNAL INPUTS (RIN, GIN, BIN) Input Amplitude 1 Black Level 2 Input Resistance Input Capacitance LOGIC INPUTS (HSYNC, VSYNC, FIN, ENCD, STND, SELECT) CMOS Logic Levels Logic LO Input Voltage Logic HI Input Voltage Logic LO Input Current ...

Page 3

... Range Description AD724JR +70 C 16-Lead SOIC AD724JR-REEL +70 C 16-Lead SOIC AD724JR-REEL7 +70 C 16-Lead SOIC AD724-EB Evaluation Board CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD724 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...

Page 4

AD724 Pin Mnemonic Description 1 STND A Logical HIGH input selects NTSC encoding. A Logical LOW input selects PAL encoding. CMOS/TTL Logic Levels. 2 AGND Analog Ground Connection. 3 FIN FSC clock or parallel-resonant crystal, or 4FSC clock input. For ...

Page 5

TEKTRONIX COMPONENT WAVEFORM GENERATOR TEKTRONIX COMPOSITE WAVEFORM GENERATOR 1.0 APL = 49.8% 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00V @ 6.63 s 0.5 0.0 SYNCHRONOUS SYNC = SOURCE FRAMES SELECTED : 1 2 –0 ...

Page 6

AD724 Figure 6. 100% Color Bars on Vector Scope, NTSC Figure 7. 100% Color Bars on Vector Scope, PAL 1.0 APL = 12.0% 525 LINE NTSC SLOW CLAMP TO 0.00V @ 6.63 s 0.5 0.0 SYNCHRONOUS –0 ...

Page 7

DG DP (NTSC) (SYNC = EXT) FIELD = 1 LINE = 27, 100 IRE RAMP DIFFERENTIAL GAIN (%) MIN = –0.53 0.00 –0.16 –0.49 –0.53 0.2 0.0 –0.2 –0.4 –0.6 –0.8 DIFFERENTIAL PHASE (deg) MIN = –1.14 0.00 –0.44 –1.14 ...

Page 8

AD724 THEORY OF OPERATION The AD724 was designed to have three allowable modes of applying a clock via the FIN pin. These are FSC (frequency of subcarrier) mode with CMOS clock applied, FSC mode using on-chip crystal oscillator, and 4FSC ...

Page 9

The filtered chrominance signal is then summed with the fil- tered luminance signal to create the composite video signal. The separate luminance, chrominance and composite video voltages are amplified by two in order to drive 75 lines. The separate luminance ...

Page 10

AD724 Both the analog and digital ground pins should be tied to the ground plane by a short, low inductance path. Each power supply pin should be bypassed to ground by a low inductance 0.1 F capacitor and a larger ...

Page 11

COMP V 24 REF FS DATA IN ADJ + ADV7120 AA 10k IOR SYNC MPEG IOG CLOCK DECODER BLANK IOB GND HSYNC VSYNC * PARALLEL–RESONANT CRYSTAL; 3.579545MHz (NTSC) OR 4.433620MHz ...

Page 12

AD724 NTSC Y2 PAL 10k 10k OPTIONAL CR1 CR2 IN4148 IN4148 U1 NOTES 3.579545MHz HC04 Figure 17. Crystal Selection Circuit Pin 1 (STND) of the AD724 is used to program the internal operation for either ...

Page 13

The VM700A has a special measurement mode that enables it to directly measure the frequency of one subcarrier in a video waveform with respect to an internally stored reference or a simultaneously supplied reference. The instrument gives a read- ing ...

Page 14

AD724 Flicker is a fundamental defect of all interlaced displays and is caused by the alternating field characteristic of the interlace technique. Consider a one pixel high black line that extends horizontally across a white screen. This line will exist ...

Page 15

REV. B OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Wide Body SOIC (R-16) 0.4133 (10.50) 0.3977 (10.00 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65 0.3937 (10.00) PIN 1 0.1043 (2.65) 0.050 ...

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