AD5764RCSUZ-REEL7 Analog Devices Inc, AD5764RCSUZ-REEL7 Datasheet - Page 23

• Manufacturer Part Number: AD5764RCSUZ-REEL7
• Description: QUAD 16-BIT +/-15V DAC
• Manufacturer: Analog Devices Inc

Specifications of AD5764RCSUZ-REEL7

• Design Resources: High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5764 (CN0006)
• Settling Time: 8µs
• Number Of Bits: 16
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 275mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

See Figure 41 for a simplified block diagram of the DAC load
circuitry.
TRANSFER FUNCTION
Table 7 and Table 8 show the ideal input code to output voltage
relationship for offset binary data coding and twos complement
data coding, respectively.
Table 7. Ideal Output Voltage to Input Code Relationship—Offset Binary Data Coding
MSB
1111
1000
1000
0111
0000
Table 8. Ideal Output Voltage to Input Code Relationship—Twos Complement Data Coding
MSB
0111
0000
0000
1111
1000
REFAB, REFCD
Figure 41. Simplified Serial Interface of Input Loading Circuitry
LDAC
SYNC
SCLK
SDIN
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
for One DAC Channel
INTERFACE
REGISTER
REGISTER
16-BIT
DAC
INPUT
LOGIC
DATA
Digital Input
Digital Input
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
I/V AMPLIFIER
OUTPUT
SDO
VOUTx
1111
0001
0000
1111
0000
1111
0001
0000
1111
0000
Rev. B | Page 23 of 32
LSB
LSB
The output voltage expression for the AD5764R is given by
where:
D is the decimal equivalent of the code loaded to the DAC.
V
REFCD pins.
ASYNCHRONOUS CLEAR (CLR)
CLR is a negative edge triggered clear that allows the outputs to
be cleared to either 0 V (twos complement coding) or negative
full scale (offset binary coding). It is necessary to maintain CLR
low for a minimum amount of time for the operation to complete
(see
remains at the cleared value until a new value is programmed.
If CLR is at 0 V at power-on, all DAC outputs are updated with
the clear value. A clear can also be initiated through software by
writing the command of 0x04XXXX.
REFIN
Analog Output
V
+2 V
+2 V
0 V
−2 V
−2 V
Analog Output
V
+2 V
+2 V
0 V
−2 V
−2 V
Figure 2
OUT
OUT
V
is the reference voltage applied at the REFAB and
OUT
REFIN
REFIN
REFIN
REFIN
REFIN
REFIN
REFIN
REFIN
=
× (1/32,768)
× (32,767/32,768)
× (1/32,768)
× (32,767/32,768)
× (32,767/32,768)
× (1/32,768)
× (32,767/32,768)
× (1/32,768)
). When the
−
2
×
V
REFIN
+
CLR signal is returned high, the output
4
×
V
REFIN
⎡
⎢
⎣
65
D
,
536
⎤
⎥
⎦
AD5764R