AD5754AREZ-REEL7 Analog Devices Inc, AD5754AREZ-REEL7 Datasheet - Page 24

• Manufacturer Part Number: AD5754AREZ-REEL7
• Description: Quad 16Bit DAC 16 Lsb INL
• Manufacturer: Analog Devices Inc

Specifications of AD5754AREZ-REEL7

• Design Resources: Software Configurable 16-Bit Quad-Channel Unipolar/Bipolar Voltage Output Using AD5754 (CN0086)
• Settling Time: 10µs
• Number Of Bits: 16
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Analog and Digital, Dual ±
• Power Dissipation (max): 310mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5724/AD5734/AD5754
INPUT SHIFT REGISTER
The input shift register is 24 bits wide and consists of a read/write bit (R/ W ), a reserved bit (zero) that must always be set to 0, three
register select bits (REG0, REG1, REG2), three DAC address bits (A2, A1, A0), and 16 data bits (data). The register data is clocked in MSB
first on the SDIN pin. Table 16 shows the register format and Table 17 describes the function of each bit in the register. All registers are
read/write registers.
Table 16. Input Register Format
MSB
DB23
R/W
Table 17. Input Register Bit Functions
Bit Mnemonic
R/W
REG2, REG1, REG0
A2, A1, A0
DB15 to DB0
DAC REGISTER
The DAC register is addressed by setting the three REG bits to 000. The DAC address bits select the DAC channel where the data transfer
is to take place (see Table 17). The data bits are in positions DB15 to DB0 for the AD5754 (see Table 18), DB15 to DB2 for the AD5734
(see Table 19), and DB15 to DB4 for the AD5724 (see Table 20).
Table 18. Programming the AD5754 DAC Register
MSB
R/W
0
Table 19. Programming the AD5734 DAC Register
MSB
R/W
0
Table 20. Programming the AD5724 DAC Register
MSB
R/W
0
Zero
0
Zero
0
Zero
0
DB22
Zero
REG2
0
Description
Indicates a read from or a write to the addressed register.
Used in association with the address bits to determine if a write operation is to the DAC register, the output range
select register, the power control register, or the control register.
REG2
0
0
0
0
These DAC address bits are used to decode the DAC channels.
A2
0
0
0
0
1
Data bits.
REG2
0
REG2
0
DB21
REG2
REG1
0
REG1
0
0
1
1
A1
0
0
1
1
0
REG1
0
REG0
0
DB20
REG1
REG0
0
1
0
1
A0
0
1
0
1
0
REG1
0
REG0
0
A2
DAC address
Function
DAC register
Output range select register
Power control register
Control register
Channel Address
DAC A
DAC B
DAC C
DAC D
All four DACs
Rev. C | Page 24 of 32
REG0
0
DB19
REG0
DAC address
A2
A1
A1
A0
DB18
A2
A2
DB15 to DB4
12-bit DAC data
A0
DAC address
DB17
A1
A1
DB15 to DB2
14-bit DAC data
A0
DB3
X
DB16
A0
DB2
X
16-bit DAC data
DB1
X
DB15 to DB0
DB15 to DB0
Data
DB1
X
LSB
DB0
X
LSB
DB0
X
LSB
LSB