AD5231BRUZ100-RL7 Analog Devices Inc, AD5231BRUZ100-RL7 Datasheet - Page 17

• Manufacturer Part Number: AD5231BRUZ100-RL7
• Description: IC,Digital Potentiometer,TSSOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD5231BRUZ100-RL7

• Taps: 1024
• Resistance (ohms): 100K
• Number Of Circuits: 1
• Temperature Coefficient: 600 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 2.7 V ~ 5.5 V, ±2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resistance In Ohms: 100K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In Table 6, command bits are C0 to C3, address bits are A3 to A0, Data Bit D0 to Data Bit D9 are applicable to RDAC, and D0 to D15 are
applicable to EEMEM.
Table 6. AD5231 24-Bit Serial Data-Word
RDAC
EEMEM
Command instruction codes are defined in Table 7.
Table 7. Command/Operation Truth Table
Instruction
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
3
4
5
5
5
5
The SDO output shifts out the last 24 bits of data clocked into the serial register for daisy-chain operation. Exception: for any instruction following Instruction 9 or
Instruction 10, the selected internal register data is present in Data Byte 0 and Data Byte 1. The instruction following 9 and 10 must also be a full 24-bit data-word to
completely clock out the contents of the serial register.
The RDAC register is a volatile scratchpad register that is refreshed at power-on from the corresponding nonvolatile EEMEM register.
Execution of these operations takes place when the CS strobe returns to logic high.
Instruction 3 writes two data bytes (16 bits of data) to EEMEM. In the case of 0 addresses, only the last 10 bits are valid for wiper position setting.
The increment, decrement, and shift instructions ignore the contents of the shift register Data Byte 0 and Data Byte 1.
4
5
5
5
5
5
MSB Command Byte 0
C3
C3
C2
C2
Command Byte 0
B23
C3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C1
C1
C2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C0
C0
C1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
A3
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
A2
A3
X
0
0
A3
0
X
0
X
X
A3
0
0
0
X
0
X
0
A1
A2
X
0
0
A2
0
X
0
X
X
A2
0
0
0
X
0
X
0
A0
1, 2, 3
A1
X
0
0
A1
0
X
0
X
X
A1
0
0
0
X
0
X
Data Byte 1
X
D15
B16
A0
X
0
0
0
X
0
X
X
A0
0
0
0
X
0
X
A0
X
D14
Data Byte 1
B15
X
X
X
X
D15
X
X
X
X
X
X
X
X
X
X
X
X
Rev. C | Page 17 of 28
X
D13
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
X
D12
D9
X
X
X
X
X
X
X
X
X
X
D9
X
X
X
X
X
D11
B8
D8
X
X
X
D8
X
X
X
X
X
X
X
D8
X
X
X
X
X
D10
Data Byte 0
B7
D7
X
X
X
X
X
X
X
X
X
X
D7
X
X
X
X
D7
D9
D9
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
D8
D8
B0
D0
X
X
X
D0
X
X
X
X
X
X
X
D0
X
X
X
X
Data Byte 0
D7
D7
Operation
NOP: Do nothing. See Table 15.
Restore EEMEM(0) contents to RDAC register.
This command leaves the device in the read
program power state. To return the part to
the idle state, perform NOP instruction 0. See
Table 15 .
Store Wiper Setting: Store RDAC setting to
EEMEM(0). See Table 14 .
16 bits) to EEMEM (ADDR 1to ADDR 15). See
Table 17 .
Decrement RDAC by 6 dB.
Same as Instruction 4.
Decrement RDAC by 1 position.
Same as Instruction 6.
Reset: Restore RDAC with EEMEM (0) value.
Read EEMEM (ADDR 0 to ADDR 15) from SDO
output in the next frame. See Table 18 .
Read RDAC wiper setting from SDO output
in the next frame. See Table 19 .
Write contents of Data Bytes 0 and 1 (total
10 bits) to RDAC. See Table 13 .
Increment RDAC by 6 dB. See Table 16.
Same as Instruction 12.
Increment RDAC by 1 position. See Table 14 .
Same as Instruction 14.
Store contents of Data Bytes 0 and 1 (total
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
AD5231
D1
D1
LSB
D0
D0