AD5170BRMZ100 Analog Devices Inc, AD5170BRMZ100 Datasheet - Page 6

• Manufacturer Part Number: AD5170BRMZ100
• Description: IC,Digital Potentiometer,TSSOP,10PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD5170BRMZ100

• Taps: 256
• Resistance (ohms): 100K
• Number Of Circuits: 1
• Temperature Coefficient: 35 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 100K
• Number Of Elements: 1
• # Of Taps: 256
• Resistance (max): 100KOhm
• Power Supply Requirement: Single
• Interface Type: Serial (2-Wire/I2C)
• Single Supply Voltage (typ): 3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5170
TIMING CHARACTERISTICS: 2.5 kΩ, 10 kΩ, 50 kΩ, AND 100 kΩ
V
Table 3.
Parameter
I
1
2
Timing Diagram
2
See Figure 2 for locations of measured values.
The maximum t
C INTERFACE TIMING CHARACTERISTICS
DD
APPLY TO ALL PARTS)
SCL Clock Frequency
t
t
t
t
t
t
t
t
t
t
OTP Program Time
BUF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
F
R
SU;STO
= 5 V ± 10% or 3 V ± 10%, V
Fall Time of Both SDA and SCL Signals
Rise Time of Both SDA and SCL Signals
Bus Free Time Between Stop and Start
Low Period of SCL Clock
High Period of SCL Clock
SDA
SCL
Setup Time for Repeated Start Condition
Setup Time for Stop Condition
Hold Time (Repeated Start)
Data Setup Time
Data Hold Time
HD;DAT
P
must be met only if the device does not stretch the low period (t
t
1
2
S
t
2
A
= V
t
3
DD
1
; V
(SPECIFICATIONS
t
8
B
t
8
= 0 V, −40°C < T
t
9
Figure 2. I
t
6
2
C Interface Detailed Timing Diagram
t
t
4
9
Rev. F | Page 6 of 24
A
< +125°C, unless otherwise noted.
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
SCL
1
2
3
4
5
6
7
8
9
10
11
LOW
t
7
) of the SCL signal.
Conditions
After this period, the first clock
pulse is generated
S
t
5
t
2
Min
1.3
0.6
1.3
0.6
0.6
100
0.6
Typ
400
P
t
10
Max
400
0.9
300
300
Unit
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
μs
ms