AD1940YSTZ Analog Devices Inc, AD1940YSTZ Datasheet
AD1940YSTZ
Specifications of AD1940YSTZ
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AD1940YSTZ Summary of contents
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FEATURES 16-channel digital audio processor Accepts sample rates up to 192 kHz 28-bit × 28-bit multiplier with full 56-bit accumulator Fully programmable program RAM for custom program download Parameter RAM allows complete control of 1,024 parameters Control port features safeload ...
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AD1940/AD1941 TABLE OF CONTENTS Specifications ..................................................................................... 3 Digital I/O ..................................................................................... 3 Power .............................................................................................. 3 Digital Timing ............................................................................... 4 PLL ................................................................................................. 5 Regulator ........................................................................................ 5 Temperature Range ...................................................................... 5 Absolute Maximum Ratings ............................................................ 6 ESD Caution .................................................................................. 6 Digital Timing Diagrams ...
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SPECIFICATIONS Test conditions, unless otherwise noted. Table 1. Parameter Supply Voltage (VDD) PLL Voltage (PLL_VDD) Output Voltage (ODVDD) INVDD Voltage Ambient Temperature Master Clock Input Load Capacitance Load Current Input Voltage, HI Input Voltage, LO DIGITAL I/O VDD = 2.25 ...
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AD1940/AD1941 DIGITAL TIMING VDD = 2.25 to 2.75 V. Specifications measured across –40°C to 125°C. 1 Table 4. Digital Timing Parameter MASTER CLOCK, SERIAL DATA PORTS, RESET MCLK Period MCLK Period MCLK Period MCLK Period MCLK Period MCLK Duty Cycle ...
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PLL VDD = 2.25 to 2.75 V. Specifications measured across –40°C to 125°C. Table 5. Parameter Lock Time REGULATOR VDD = 2.25 to 2.75 V. Specifications measured across –40°C to 125°C. Table 6. Parameter VSENSE Output Voltage TEMPERATURE RANGE Table ...
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AD1940/AD1941 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Min VDD to DGND –0.3 PLL_ VDD to PGND –0.3 OD VDD to DGND –0.3 INVDD to DGND ODVDD Digital Inputs DGND – 0.3 Maximum Junction Temperature Storage Temperature –65 Range Soldering (10 ...
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DIGITAL TIMING DIAGRAMS t BIH BCLK_IN t BIL t LIS LRCLK_IN t SIS SDATA_INX LEFT-JUSTIFIED MSB MODE t SIH SDATA_INX 2 I S-JUSTIFIED MODE SDATA_INX RIGHT-JUSTIFIED MODE 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 14-BIT CLOCKS (18-BIT DATA) 16-BIT ...
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AD1940/AD1941 t CLS CLATCH CCLK CDATA t CDS COUT SDA SCLK t MCLK RESETB t CCPL t CCPH t CDH Figure 4. AD1940 SPI Port Timing TSCH SCLH SCS SCLL ST ...
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD 1 PIN 1 INDICATOR MCLK 2 RESERVED 3 PLL_CTRL0 4 PLL_CTRL1 5 AD1940 PLL_CTRL2 6 TOP VIEW PLL_GND 7 (Not to Scale) PLL_VDD 8 NC ...
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AD1940/AD1941 Pin No. AD1940 AD1941 I IN/OUT IN/OUT 27 27 IN/OUT 28, 33, 40 28, 33 OUT 30 30 OUT 31 31 OUT 32 32 OUT 34 ...
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FEATURES The core of the AD1940/AD1941 is a 28-bit DSP (56-bit, double precision) optimized for audio processing. The parts’ program RAM can be loaded with a custom program after power-up. Signal processing parameters are stored in a 1024 location parameter ...
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AD1940/AD1941 PIN FUNCTIONS Table 10 shows the AD1940/AD1941’s pin numbers, names, and functions. Input pins have a logic threshold compatible with TTL input levels and may be used in systems with 3 logic. SDATA_IN0 SDATA_IN1 SDATA_IN2/TDM_IN1 ...
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I C_FILT_ENB (AD1941 Spike Filter Enable/Disable. This enables (active low) the I spike filter, which is used to prevent noise or glitches on the I bus from improperly affecting the AD1941. ADR_SEL Address Select. This pin ...
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AD1940/AD1941 SIGNAL PROCESSING OVERVIEW The AD1940/AD1941 are designed to provide all signal processing functions commonly used in stereo or multichannel playback systems. The signal processing flow is set by using the ADI-supplied software, which allows graphical entry and real- time ...
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CONTROL PORT OVERVIEW The AD1940/AD1941 have many different control options that 2 can be set through an SPI interface. The AD1940 uses a 4-wire SPI control port and the AD1941 uses a 2-wire I control port. Most ...
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AD1940/AD1941 of the byte sets either a read or write operation; Logic Level 1 corresponds to a read operation and Logic Level 0 corresponds to a write operation. The seventh bit of the address is set by tying the ADR_SEL ...
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CLATCH CCLK MSB BYTE 0 CDATA CLATCH CCLK BYTE 0 BYTE 1 CDATA HI-Z COUT SCK SDA START BY MASTER FRAME 1 CHIP ADDRESS BYTE 1 SCK (CONTINUED) SDA (CONTINUED) FRAME 3 SUBADDRESS BYTE 2 LSB ...
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AD1940/AD1941 SCK SDA START BY MASTER FRAME 1 CHIP ADDRESS BYTE 1 SCK (CONTINUED) SDA (CONTINUED) FRAME 3 SUBADDRESS BYTE 2 SCK (CONTINUED) SDA (CONTINUED) FRAME 5 READ DATA BYTE 1 2 Table 13. Single Word I C Write S ...
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RAMS AND REGISTERS Table 17. Control Port Addresses 2 SPI Subaddress Register Name 0–1023 (0x0000–0x03FF) Parameter RAM 1024–2559 (0x0400–0x09FF) Program RAM 2560–2623 (0x0A00–0x0A3F) Target/Slew RAM 2624–2628 (0x0A40–0x0A44) Parameter RAM Data Safeload Registers 0–4 2629–2633 (0x0A45–0x0A49) Parameter RAM Indirect ...
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AD1940/AD1941 RECOMMENDED PROGRAM/PARAMETER LOADING PROCEDURES When writing large amounts of data to the program or para- meter RAM in direct write mode, the processor core should be disabled to prevent unpleasant noises from appearing at the audio output. The AD1940/AD1941 ...
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The four ramping curve types are • Linear—Value slews to target using a fixed step size. • Constant dB—Value slews to target using the current value to calculate the step size. The resulting curve has a constant rise and decay ...
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AD1940/AD1941 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 TIME (ms) Figure 16. Slew RAM—Linear Update Decreasing Ramp Constant dB and RC Type (Exponential) Update Math Exponential math is accomplished by shifts ...
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TIME (ms) Figure 21. Slew RAM—Constant Time Update Increasing Ramp, Half Scale 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 ...
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AD1940/AD1941 counter equals the capture count. The register select field selections are shown in Table 23. Table 23. Data Capture Output Register Select Setting Register 00 Multiplier X input (Mult_X_input) 01 Multiplier Y input (Mult_Y_input) 10 Multiplier-Accumulator Output (MAC_out) 11 ...
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Initialize Data Memory with Zeros (Bit 7) Setting this bit to 1 initializes all data memory locations to 0. This bit is cleared to 0 after the operation is complete. This bit should be asserted after a complete program/parameter download ...
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AD1940/AD1941 The total number of bytes for a single location write command can vary from four bytes (for a control register write), to eight bytes (for a program RAM write). Burst mode may be used to fill contiguous register or ...
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Table 32. Data Capture Register Write Format Byte 0 Byte 1 chip_adr [6:0], W/R 0000, data_capture_adr [11:8] 1 Progcount [10:0] = value of program counter where trap occurs (the table of values is generated by the program compiler). 2 Regsel ...
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AD1940/AD1941 SERIAL DATA INPUT/OUTPUT PORTS The AD1940/AD1941’s flexible serial data input and output ports can be set to accept or transmit data in 2-channel formats 16-channel TDM stream. Data is processed in twos complement, MSB ...
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Table 38. Serial Output Control Register 1 (Channels 0–7) (2644) Bits Function 15 Dither enable 0 = Diabled 1 = Enabled 14 Internally link TDM streams into single, 16-channel stream 0 = Indepenent 1 = Linked 13 LRCLK polarity 0 ...
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AD1940/AD1941 SERIAL OUTPUT CONTROL REGISTERS Dither Enable (Bit 15) Setting this bit to 1 enables dither on the appropriate channels. Internally Link TDM Streams into Single 16-Channel Stream (Bit 14, Serial Output Control Register 1) When this bit is set ...
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BCLK Polarity (Bit 3) This bit controls on which edge of the bit clock the input data changes, and on which edge it is clocked. Data changes on the falling edge of BCLK_IN when this bit is set to 0, ...
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AD1940/AD1941 LRCLK BCLK DATA LRCLK BCLK MSB TDM SDATA CH 0 SLOT 0 SLOT 1 32 BCLKs 256 BCLKs 32 BCLKs SLOT 0 SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 LRCLK BCLK DATA MSB MSB–1 MSB–2 Figure ...
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INITIALIZATION POWER-UP SEQUENCE The AD1940/AD1941 have a built-in power-up sequence that initializes the contents of all internal RAMs. During this time, the contents of the internal program boot ROM are copied to the internal program RAM memory and the parameter ...
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AD1940/AD1941 There are two specifications that should be taken into consideration when choosing a regulator transistor. First, the transistor’s current amplification factor (h at least 100. Second, the transistor’s collector needs to be able to dissipate the heat generated when ...
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... SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE 1 Model Temperature Range AD1940YSTZ –40°C to +105°C AD1940YSTZRL –40°C to +105°C AD1941YSTZ –40°C to +105°C AD1941YSTZRL –40°C to +105°C Eval-AD1940AZ Eval-AD1940MINIBZ RoHS Compliant Part. 9.20 9.00 SQ 0.75 1 ...
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AD1940/AD1941 NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Patent Rights to use these components ...