5M1270ZT144C4N Altera, 5M1270ZT144C4N Datasheet - Page 108

• Manufacturer Part Number: 5M1270ZT144C4N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M1270ZT144C4N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of Gates: -
• Number Of I /o: 114
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

7–6
Figure 7–3. UFM Data Register
MAX V Device Handbook
DRDin
UFM Data Register
UFM Program/Erase Control Block
LSB
D0
The UFM data register is 16 bits wide with four control signals: DRSHFT, DRCLK, DRDin,
and DRDout. DRSHFT distinguishes between clock edges that move data serially from
DRDin to DRDout and clock edges that latch parallel data from the UFM sectors. If the
DRSHFT signal is high, a clock edge moves data serially through the registers from
DRDin to DRDout. If the DRSHFT signal is low, a clock edge captures data from the UFM
sector pointed by the address register in parallel. The MSB is the first bit that is seen at
DRDout. The data register DRSHFT signal is also used to enable the UFM for reading
data. When the DRSHFT signal is low, the UFM latches data into the data register.
Figure 7–3
The UFM program/erase control block is used to generate all the control signals
necessary to program and erase the UFM block independently. This block reduces the
number of logic elements (LEs) necessary to implement a UFM controller in the logic
array. It also guarantees correct timing of the control signals to the UFM. A rising edge
on either PROGRAM or ERASE signal causes this control signal block to activate and begin
sequencing through the program or erase cycle. At this point, for a program
instruction, the data currently in the data register is written to the address pointed to
by the address register.
Only sector erase is supported by the UFM. When an ERASE command is executed,
this control block erases the sector whose address is stored in the address register.
When the PROGRAM or ERASE command first activates the program/erase control
block, the BUSY signal will be driven high to indicate an operation in progress in the
UFM. After the program or erase algorithm is completed, the BUSY signal is forced
low.
D1
D2
D3
shows the UFM data register.
D4
D5
D6
16
MAX V UFM Block
D7
Data Register
D8
D9
D10
16
D11
Chapter 7: User Flash Memory in MAX V Devices
D12
D13
January 2011 Altera Corporation
D14
UFM Functional Description
MSB
D15
DRDout
DRCLK