25AA512-I/MF Microchip Technology, 25AA512-I/MF Datasheet - Page 17
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25AA512-I/MF
Manufacturer Part Number
25AA512-I/MF
Description
512k, 64K X 8 , 1.8V SER EE IND 8 DFN-S 6X5MM TUBE
Manufacturer
Microchip Technology
Datasheet
1.25AA512-ISN.pdf
(36 pages)
Specifications of 25AA512-I/MF
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
512K (64K x 8)
Speed
20MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
25AA512-I/MF
Manufacturer:
MICROCHIP
Quantity:
12 000
Part Number:
25AA512-I/MF
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
2.10
The CHIP ERASE instruction will erase all bits (FFh) in
the array. A Write Enable (WREN) instruction must be
given prior to executing a CHIP ERASE. This is done
by setting CS low and then clocking out the proper
instruction into the 25AA512. After all eight bits of the
instruction are transmitted, the CS must be brought
high to set the write enable latch.
The CHIP ERASE instruction is entered by driving the
CS low, followed by the instruction code (Figure 2-10)
onto the SI line.
FIGURE 2-10:
2010 Microchip Technology Inc.
CHIP ERASE
CHIP ERASE SEQUENCE
SCK
CS
SO
SI
1
0
1
1
High-Impedance
0
2
0
3
The CS pin must be driven high after the eighth bit of
the instruction code has been given or the CHIP
ERASE instruction will not be executed. Once the CS
pin is driven high the self-timed CHIP ERASE instruc-
tion begins. While the device is executing the CHIP
ERASE instruction the WIP bit in the STATUS register
can be read to determine when the CHIP
instruction is complete.
The CHIP ERASE instruction is ignored if either of the
Block Protect bits (BP0, BP1) are not 0, meaning ¼,
½, or all of the array is protected.
0
4
1
5
1
6
1
7
25AA512
DS22021F-page 17
ERASE