24LC024H-E/SN Microchip Technology, 24LC024H-E/SN Datasheet - Page 11

• Manufacturer Part Number: 24LC024H-E/SN
• Description: 2K, 256 X 8 SERIAL EE, EXT, 1/2 ARRAY WP 8 SOIC 3.90mm (.150") TUBE
• Manufacturer: Microchip Technology

Specifications of 24LC024H-E/SN

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.0
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
The 24AA024H/24LC024H contains an address
counter that maintains the address of the last word
accessed, internally incremented by one. Therefore, if
the previous read access was to address n, the next
current address read operation would access data from
address n + 1. Upon receipt of the slave address with
the R/W bit set to ‘1’, the 24AA024H/24LC024H issues
an acknowledge and transmits the 8-bit data word. The
master will not acknowledge the transfer, but does
generate a Stop condition and the 24AA024H/
24LC024H discontinues transmission (Figure 8-1).
8.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is done by sending the word address to the
24AA024H/24LC024H as part of a write operation.
FIGURE 8-1:
© 2008 Microchip Technology Inc.
READ OPERATIONS
Current Address Read
Random Read
CURRENT ADDRESS READ
Bus Activity
Master
SDA Line
Bus Activity
S
A
R
T
T
S
Control
Byte
24AA024H/24LC024H
C
A
K
Once the word address is sent, the master generates a
Start condition following the acknowledge. This
terminates the write operation, but not before the
internal Address Pointer is set. The master then issues
the control byte again but with the R/W bit set to a ‘1’.
The
acknowledge and transmits the eight-bit data word.
The master will not acknowledge the transfer, but does
generate a Stop condition and the 24AA024H/
24LC024H discontinues transmission (Figure 8-2).
After this command, the internal address counter will
point to the address location following the one that was
just read.
8.3
Sequential reads are initiated in the same way as a
random read except that after the 24AA024H/
24LC024H transmits the first data byte, the master
issues an acknowledge as opposed to a Stop condition
in a random read. This directs the 24AA024H/
24LC024H to transmit the next sequentially addressed
8-bit word (Figure 8-3).
To provide sequential reads, the 24AA024H/24LC024H
contains an internal Address Pointer which is
incremented by one at the completion of each
operation. This Address Pointer allows the entire
memory contents to be serially read during one
operation. The
automatically roll over from address FFh to address
00h.
Data
24AA024H/24LC024H
Sequential Read
O
K
N
A
C
O
P
S
T
P
internal
Address
will
DS22102A-page 11
then
Pointer
issue
will
an