XCS30-3PQ240C Xilinx Inc, XCS30-3PQ240C Datasheet - Page 37
![no-image](/images/no-image-200.jpg)
XCS30-3PQ240C
Manufacturer Part Number
XCS30-3PQ240C
Description
INTERGRATED CIRCUIT
Manufacturer
Xilinx Inc
Series
Spartan™r
Datasheet
1.XCS05XL-4VQG100C.pdf
(83 pages)
Specifications of XCS30-3PQ240C
Number Of Logic Elements/cells
1368
Number Of Labs/clbs
576
Total Ram Bits
18432
Number Of I /o
192
Number Of Gates
30000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-BFQFP
Case
QFP240
Dc
01+/04+
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XCS30-3PQ240C
Manufacturer:
XILINX
Quantity:
1 238
Company:
Part Number:
XCS30-3PQ240C
Manufacturer:
XilinxInc
Quantity:
3 000
Part Number:
XCS30-3PQ240C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Configuration Through the Boundary Scan
Pins
Spartan/XL devices can be configured through the bound-
ary scan pins. The basic procedure is as follows:
•
•
DS060 (v1.8) June 26, 2008
Product Specification
Power up the FPGA with INIT held Low (or drive the
PROGRAM pin Low for more than 300 ns followed by a
High while holding INIT Low). Holding INIT Low allows
enough time to issue the CONFIG command to the
FPGA. The pin can be used as I/O after configuration if
a resistor is used to hold INIT Low.
Issue the CONFIG command to the TMS input.
R
CCLK_NOSYNC
UCLK_NOSYNC
CCLK_SYNC
UCLK_SYNC
CCLK
Synchronization
Uncertainty
DONE
I/O
DONE
I/O
DONE
I/O
DONE
I/O
GSR Active
GSR Active
GSR Active
GSR Active
Length Count Match
C1, C2 or C3
DONE IN
C1
C1
C1
Di
Figure 31: Start-up Timing
Di
DONE IN
Di+1
Di+1
C2
C2
C2
www.xilinx.com
U2
U2
U2
U2
Di
UCLK Period
Di
Di+1
Di+1
•
•
•
The user must account for all TCK clock cycles after INIT
goes High, as all of these cycles affect the Length Count
compare.
For more detailed information, refer to the Xilinx application
note, "Boundary Scan in FPGA Devices." This application
note applies to Spartan and Spartan-XL devices.
U3
U3
U3
C3
C3
C3
Wait for INIT to go High.
Sequence the boundary scan Test Access Port to the
SHIFT-DR state.
Toggle TCK to clock data into TDI pin.
Spartan and Spartan-XL FPGA Families Data Sheet
CCLK Period
Di+2
Di+2
U4
U4
U4
F
F
F
C4
C4
C4
F
F = Finished, no more
configuration clocks needed
Daisy-chain lead device
must have latest F
Heavy lines describe
default timing
DS060_39_082801
37