XCF01SVOG20C Xilinx Inc, XCF01SVOG20C Datasheet - Page 20

• Manufacturer Part Number: XCF01SVOG20C
• Description: INTERGRATED CIRCUIT
• Manufacturer: Xilinx Inc

Specifications of XCF01SVOG20C

• Programmable Type: In System Programmable
• Memory Size: 1Mb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-TSSOP (0.173", 4.40mm Width)
• Memory Type: Flash
• Interface Type: Serial, Parallel, JTAG
• Clock Frequency: 50MHz
• Supply Voltage Range: 2.3V To 2.7V, 3V To 3.6V
• Memory Case Style: TSSOP
• No. Of Pins: 20
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1286-5

DS123 (v2.18) May 19, 2010
Product Specification
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. When decompression is enabled, the CLKOUT signal becomes a controlled clock output. When decompressed data is available, CLKOUT
11. When JTAG CONFIG command is issued, PROM drives CF Low for at least the T
T
T
T
HXT
SRV
HRV
Symbol
AC test load = 50 pF for XCF01S/XCF02S/XCF04S; 30 pF for XCF08P/XCF16P/XCF32P.
Float delays are measured with 5 pF AC loads.Transition is measured at ±200 mV from steady-state active levels.
Guaranteed by design, not tested.
All AC parameters are measured with V
If T
If T
This is the minimum possible T
at 3.3V, if FPGA Data setup time = 15 ns, then the actual T
The delay before the enabled CLKOUT signal begins clocking data out of the device is dependent on the clocking configuration. The delay
before CLKOUT is enabled increases if decompression is enabled.
Slower CLK frequency option might be required to meet the FPGA data sheet setup time.
toggles at ½ the source clock frequency (either ½ the selected internal clock frequency or ½ the external CLK input frequency). When
decompressed data is not available, the CLKOUT pin is parked High. If CLKOUT is used, then it must be pulled High externally using a
4.7 kΩ pull-up to V
HCE
HOE
High < 2 µs, T
Low < 2 µs, T
R
EN_EXT_SEL hold time from CF, CE, or OE/RESET when V
EN_EXT_SEL hold time from CF, CE, or OE/RESET when V
REV_SEL setup time to CF, CE, or OE/RESET when V
REV_SEL setup time to CF, CE, or OE/RESET when V
REV_SEL hold time from CF, CE, or OE/RESET when V
REV_SEL hold time from CF, CE, or OE/RESET when V
CCO
CE
OE
.
= 2 µs.
= 2 µs.
CYCO
. Actual T
IL
= 0.0V and V
CYCO
Description
= T
CCDD
IH
= 3.0V.
www.xilinx.com
CYCO
Platform Flash In-System Programmable Configuration PROMs
+ FPGA Data setup time. Example: With the XCF32P in serial mode with V
= 25 ns +15 ns = 40 ns.
CCO
CCO
CCO
CCO
= 3.3V or 2.5V
= 1.8V
CCO
CCO
= 3.3V or 2.5V
= 1.8V
= 3.3V or 2.5V
= 1.8V
HCF
minimum.
XCF08P, XCF16P,
Min
300
300
300
300
300
300
XCF32P
Max
–
–
–
–
–
–
Units
ns
ns
ns
ns
ns
ns
CCO
20