XC2C256-7TQG144I Xilinx Inc, XC2C256-7TQG144I Datasheet - Page 10

• Manufacturer Part Number: XC2C256-7TQG144I
• Description: CPLD, COOLRUNNER-II, 256MCELL 144TQFP
• Manufacturer: Xilinx Inc
• Series: XC2C256r

Specifications of XC2C256-7TQG144I

• No. Of Macrocells: 256
• No. Of I/o's: 118
• Propagation Delay: 5.7ns
• Global Clock Setup Time: 2.4ns
• Frequency: 256MHz
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature: RoHS Compliant
• Features: Programmable
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage: 1.8V
• Number Of I /o: 118
• Memory Type: CMOS
• Programmable Type: In System Programmable
• Number Of Macrocells: 256
• Delay Time Tpd(1) Max: 7.5nS
• Voltage Supply - Internal: 1.7 V ~ 1.9 V
• Number Of Logic Elements/blocks: 16
• Number Of Gates: 6000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With: 122-1573 - KIT STARTER COOLRUNNER-II LP/LC122-1512 - KIT DESIGN CPLD W/BATT HOLDER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CoolRunner-II CPLD Family
Design Security
Designs can be secured during programming to prevent
either accidental overwriting or pattern theft via readback.
Four independent levels of security are provided on-chip,
10
Figure 10: CoolCLOCK Created by Cascading Clock Divider and DualEDGE Option
Figure 9: Macrocell Clock Chain with DualEDGE Option Shown
Synch Reset
CLK_CT
PTC
GCK2
CTC
PTC
GCK0
GCK1
GCK2
GCK0
GCK1
GCK2
www.xilinx.com
Clock
In
Synch Rst
eliminating any electrical or visual detection of configuration
patterns. These security bits can be reset only by erasing
the entire device. See
÷10
÷12
÷14
÷16
÷2
÷4
÷6
÷8
PTC
PTC
D/T
CE
CK
D/T
CE
CK
✓
DS090_09_121201
✓
FIF
Latch
DualEDGE
FIF
Latch
DualEDGE
WP170
Q
DS090 (v3.1) September 11, 2008
Q
for more detail.
Product Specification
R