5M2210ZF256C5N Altera, 5M2210ZF256C5N Datasheet - Page 112

• Manufacturer Part Number: 5M2210ZF256C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M2210ZF256C5N

• Cpld Type: FLASH
• No. Of Macrocells: 1700
• No. Of I/o's: 271
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 201.1MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 2210
• Number Of Macrocells: 1700
• Number Of Gates: -
• Number Of I /o: 203
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LBGA
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

7–10
Figure 7–7. UFM Program Waveforms
MAX V Device Handbook
Program
PROGRAM
OSC_ENA
ARSHFT
DRSHFT
DRDout
ARCLK
DRCLK
ERASE
DRDin
ARDin
BUSY
To program or write to the UFM, you must first perform a sequence to load the
reference address into the address register. DRSHFT must then be asserted high to load
the data serially into the data register starting with the MSB. Loading an address into
the address register and loading data into the data register can be done concurrently.
After the 16 bits of data have been successfully shifted into the data register, the
PROGRAM signal must be asserted high to start writing to the UFM. On the rising edge,
the data currently in the data register is written to the location currently in the address
register. The BUSY signal is asserted until the program sequence is completed. The data
and address register should not be modified until the BUSY signal is de-asserted, or the
flash content will be corrupted. The PROGRAM signal is ignored if the BUSY signal is
asserted. When the PROGRAM signal is applied at exactly the same time as the ERASE
signal, the behavior is undefined and the flash content is corrupted.
the UFM waveforms during program mode.
t
t
ADS
ASU
t
ACLK
9 Address Bits
t
t
ADH
AH
t
t
DSS
DDS
t
DCLK
16 Data Bits
t
DDH
Chapter 7: User Flash Memory in MAX V Devices
t
PB
t
OSCS
t
DSH
January 2011 Altera Corporation
t
PPMX
t
OSCH
Figure 7–7
UFM Operating Modes
t
BP
shows