EMA6DXV5T5 ON Semiconductor, EMA6DXV5T5 Datasheet - Page 3

• Manufacturer Part Number: EMA6DXV5T5
• Description: Digital Transistors 100mA 50V BRT PNP
• Manufacturer: ON Semiconductor

Specifications of EMA6DXV5T5

• Configuration: Dual Common Emitter
• Transistor Polarity: PNP
• Typical Input Resistor: 47 KOhms at NPN, 4.7 KOhms at PNP
• Typical Resistor Ratio: 1 at NPN, 0.47 at PNP
• Mounting Style: SMD/SMT
• Package / Case: SOT-553-5
• Collector- Emitter Voltage Vceo Max: 50 V
• Continuous Collector Current: 0.1 A
• Peak Dc Collector Current: 100 mA
• Power Dissipation: 230 mW
• Maximum Operating Temperature: + 150 C
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
the pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipa-
tion. Power dissipation for a surface mount device is deter-
mined by T
of the die, R
junction to ambient, and the operating temperature, T
Using the values provided on the data sheet for the
SOT−553 package, P
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature T
one can calculate the power dissipation of the device which
in this case is 150 milliwatts.
of the recommended footprint on a glass epoxy printed
circuit board to achieve a power dissipation of 150 milli-
watts. There are other alternatives to achieving higher
power dissipation from the SOT−553 package. Another
alternative would be to use a ceramic substrate or an
aluminum core board such as Thermal Clad . Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
Surface mount board layout is a critical portion of the
The power dissipation of the SOT−553 is a function of
The values for the equation are found in the maximum
The 833 C/W for the SOT−553 package assumes the use
INFORMATION FOR USING THE SOT−553 SURFACE MOUNT PACKAGE
P
J(max)
D
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
qJA
=
, the thermal resistance from the device
150 C − 25 C
, the maximum rated junction temperature
833 C/W
P
D
D
=
can be calculated as follows:
T
J(max)
R
qJA
= 150 milliwatts
− T
A
EMA6DXV5T1, EMA6DXV5T5
SOT−553 POWER DISSIPATION
0.0531
1.35
A
of 25 C,
http://onsemi.com
0.0197
SOT−553
A
0.5
0.0118
.
0.3
0.0394
1.0
3
0.0197
0.5
rated temperature of the device. When the entire device is
heated to a high temperature, failure to complete soldering
within a short time could result in device failure. There-
fore, the following items should always be observed in
order to minimize the thermal stress to which the devices
are subjected.
* Soldering a device without preheating can cause exces-
sive thermal shock and stress which can result in damage
to the device.
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
The melting temperature of solder is higher than the
soldering should be 100 C or less.*
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10 C.
260 C for more than 10 seconds.
maximum temperature gradient shall be 5 C or less.
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
during cooling.
Always preheat the device.
The delta temperature between the preheat and
When preheating and soldering, the temperature of the
The soldering temperature and time shall not exceed
When shifting from preheating to soldering, the
After soldering has been completed, the device should
Mechanical stress or shock should not be applied
0.0177
0.45
inches
mm
SOLDERING PRECAUTIONS