ZIC2410-EDK-1 CEL, ZIC2410-EDK-1 Datasheet
ZIC2410-EDK-1
Specifications of ZIC2410-EDK-1
Related parts for ZIC2410-EDK-1
ZIC2410-EDK-1 Summary of contents
Page 1
... UART and is one of the first devices to provide an embedded Voice CODEC. This chip is ideal for very low power applications. The ZIC2410 is available in two industry standard packages: a 48-pin QFN (7x7mm 72-pin VFBGA (5x5mm) package. CEL provides its customers with the CEL ZigBee Stack, software in a compiled library, as well as all the hardware & ...
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... Internal RC oscillator for Sleep Timer On-chip Power-on-Reset Ordering Part Number Description ZIC2410QN48R 48-pin QFN Package (T/R) ZIC2410FG72R 72-pin VFBGA Package (T/R) ZIC2410-EDK-1 Demonstration Kit FEATURES 4-channel 8-bit ADC SPI Master/Slave Interface ISP (In System Programming) Internal Temperature Sensor Clock Inputs 16MHz Crystal for System Clock (optional 19 ...
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... DATA ENCRYPTION AND DECRYPTION .......................................... 60 1.9 PHYSICAL LAYER (PHY) ................................................................ 66 1.9.1 INTERRUPT ....................................................................................... 68 1.9.2 REGISTERS ....................................................................................... 68 1.10 IN-SYSTEM PROGRAMMING (ISP) ................................................ 88 1.11 ZIC2410 INSTRUCTION SET SUMMARY ....................................... 89 1.12 DIGITAL I/O ...................................................................................... 92 & DC CHARACTERISTICS ............................................ 93 2.1 ABSOLUTE MAXIMUM RATINGS ................................................... 93 ...
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... QN48 Package ................................................................................. 101 3.1.2 FG72 Package .................................................................................. 104 3.2 PACKAGE INFORMATION ............................................................ 107 3.2.1 PACKAGE INFORMATION: ZIC2410QN48 (QN48pkg) .................. 107 3.2.2 PACKAGE INFORMATION: ZIC2410FG72 (FG72pkg) ................... 110 3.3 APPLICATION CIRCUITS ............................................................... 112 3.3.1 APPLICATION CIRCUITS (QN48 package) ..................................... 112 ...
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... FUNCTIONAL DESCRIPTION Figure 1 shows the block diagram of ZIC2410. The ZIC2410 consists of a 2.4GHz RF, Modem (PHY Layer), a MAC hardware engine, a Voice CODEC block, Clocks, Peripherals, and a memory and Microcontroller (MCU) block. Figure 1 – Functional Block Diagram of ZIC2410 Note: The ZIC2410QN48 has 22 GPIOs; the ZIC2410FG72 has 24. ...
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... The data memory has 2 memory areas. For more detailed explanation, refer to the data memory section (1.2.2.) The ZIC2410 includes 22 GPIO for the QN48 packaged device and 24 GPIO for the FG72 packaged part and various peripheral circuits to aid in the development of an application circuit with an interrupt handler to control the peripherals ...
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... ENROM = 1 (AFTER RESET) Figure 2 – Address Map of Program Memory ZIC2410 includes non-volatile memory of 96KB. However, as described already, program memory area is 64KB. Therefore, if necessary, the upper 64KB of physical 96KB non-volatile memory is separated into two 32KB memory banks. Each bank is logically mapped to the program memory. When FBANK value is ‘ ...
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... Low 32KB (0x00000~0x07FFF) FBANK=0 Figure 3 – Bank Selection of Program Memory 1.2.2 DATA MEMORY ZIC2410 reserves data memory address space. This address space can be accessed by the MOVX command. Figure 4 shows the address map of this data memory. Rev A ZIC2410 Datasheet Upper 32KB ...
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... The address space above the bank area is the bit addressable area, which is used as a flag by software bit operation. The address space above the bit addressable area includes registers used as a general purpose of a byte unit. For the detailed information, refer to the paragraphs following Figure 5 below. Rev A ZIC2410 Datasheet Document No. 0005-05-07-00-000 Page 9 of 119 ...
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... Table 1 – Special Function Register (SFR) Map Register SFR B7 B6 Name Address EIP 0xF8 VCEIP B 0xF0 EIE 0xE8 VCEIE Rev A ZIC2410 Datasheet SFR Data RAM Area GPR Bank3 Bank2 Bank1 Bank0 Figure 5 – GPRs Address Map SPIIP RTCIP T3IP AESIP ...
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... TF1 TR1 PCON 0x87 P0SEL 0x85 P0MSK 0x84 DPH 0x83 DPL 0x82 SP 0x81 P0 0x80 The following section describes each SFR related to microprocessor. Symbol RW RO Rev A ZIC2410 Datasheet RTCIF WDTWE WDTEN WDTCLR ISPMODE PS0 PT1 PX1 TR3 M3 ES0 ET1 EX1 T2IF ...
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... This register value is increased before the data is stored and the register value is decreased after the data is read when the data of stack is disappeared by POP and RET command. The default value is 0x07. 7:0 Stack Pointer SP Rev A ZIC2410 Datasheet Table 3 – Special Function Registers Descriptions Document No. 0005-05-07-00-000 Reset R/W ...
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... This port register is used as a general purpose I/O port. P3.4 When Timer0 is operated as a COUNTER mode operated as / counter input signal (T0) of Timer0. When port register is used as UART0 used as a RTS signal /RTS0 (RTS0) of UART0. Rev A ZIC2410 Datasheet Descriptions Document No. 0005-05-07-00-000 Reset R/W Value R/W 0x00 R/W 0x00 ...
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... Sleep Timer, by setting the /RTXTALI PHY register. This port register is used as a general purpose I/O port. P1.3 3 When this port register is used as QUAD function used as /QUADZA the input signal of ZA value. Rev A ZIC2410 Datasheet Descriptions Document No. 0005-05-07-00-000 Reset R/W Value R/W 1 R/W 1 ...
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... P0OEN, P1OEN and P3OEN enable the output of port0, 1 and 3. When each bit is cleared to ‘0’, the output of the corresponding port is enabled. For example, when 4 of port1.3 is enabled. 7 Reserved Rev A ZIC2410 Datasheet Descriptions th bit of P1OEN is set to low, the output Document No. 0005-05-07-00-000 Reset ...
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... When this field is set to ‘1’, P0 and P0MSK are ORed per bit. The 0 bits of the result value are to be ANed and then output to P1.7. P0AndSel This function is used to implement remote control function. Rev A ZIC2410 Datasheet Descriptions Document No. 0005-05-07-00-000 Reset R/W Value ...
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... RESET The ZIC2410 should be reset to be operated. There are three kinds of reset sources. The first one is to use an external reset pin (RESET#). When applying a low signal to this pin for more than 1ms, ZIC2410 is reset. Second, ZIC2410 can be reset by an internal POR when it is powered up as using the internal Power-On-Reset (POR) block ...
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... Circuit by adjusting ELM7527NB] Figure 7 – Reset Circuit Using ELM7527NB Checking the RESET-IC Circuit 1. In the application circuit of ZIC2410, please connect RESET# PIN to Pull-up register and should not connect it to capacitor. 2. When applying RESET-IC, detection voltage should be set over 1.9V. 3. The interval (T_reset) until from the time which reset signal by Reset IC has been adjusted to the time which the voltage of VDD (3 ...
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... CLOCK SOURCE The ZIC2410 can use either a 16MHz or a 19.2MHz crystal as the system clock source. An external 32.768 KHz crystal or the internal clock generated from internal the RCOSC is used for the Sleep Timer clock. For the internal 8051 MCU Clock in the ZIC2410, either 8MHz or 16MHz can be used. When selecting the 8051 MCU Clock (8MHz, 16MHz), the CLKDIV0 register should be set as follows ...
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... The ZIC2410 has 13 interrupt sources. Table 6 describes the detailed information for each of the interrupt sources. The ‘Interrupt Address’ indicates the address where the interrupt service routine is located. The ‘Interrupt Flag’ is the bit that notifies the MCU that the corresponding interrupt has occurred. ‘ ...
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... Interrupt disabled RTCIE 1: Interrupt enabled Timer3 Interrupt Enable 3 0: Interrupt disabled T3IE 1: Interrupt enabled AES Interrupt Enable 2 0: Interrupt disabled AESIE 1: Interrupt enabled Rev A ZIC2410 Datasheet Table 7 – INTERRUPT Registers Descriptions Document No. 0005-05-07-00-000 Reset R/W Value R R/W 0 R/W ...
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... Reserved 1.6 POWER MANAGEMENT There are three Power-Down modes in the ZIC2410. Each mode can be set by PDMODE [1:0] bits in PDCON (0x22F1) register and Power-Down mode can be started by setting PDSTART bit to 1. Each mode has a different current consumption and different wake-up sources. Table 8 describes the three Power-Down modes ...
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... In the case of PM1 and PM2,the minimum time until the system is operating after going into the Power Down mode, is around 534μsec (RTINT:0x01, RTDLY:0x11). Figure 9 – Sleep Timer Interrupt: Wake Up Times Rev A ZIC2410 Datasheet Table 8 – Power Down Modes Regulator for Digital Wake-Up Source ...
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... IDLE bit is cleared and the device exits from the IDLE mode. The required interrupt service routine is then executed and the next instruction (after the instruction setting IDLE to ‘1’) is executed. Rev A ZIC2410 Datasheet Based on the CEL' reference circuit. DVREG Main OSC ...
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... When this field is set to ‘1’, all the clocks in MCU except peripherals IDLE are stopped. Only peripherals operate normally. When ZIC2410 goes into Power-Down mode by setting PDSTART field of PDM register, PD bit of PCON register should also be set into PD (Power-Down) mode, PDMODE field should be set After that, PD bit of PCON register should be set the following instruction that set PDMODE ...
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... ONCHIP PERIPHERALS On-chips peripherals in ZIC2410 are as follows. • TIMER 0/1 • TIMER 2/3,PWM 2/3 • Watch-dog timer • Sleep Timer • Internal RC Oscillator for Sleep Timer • Two High-Speed UARTs with Two 16-byte FIFOs (up to 1Mbps) • SPI Master/Slave Interface • ...
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... In mode0, the 12-bit register of timer0 consists of 7-bit of TH0 and the lower 5-bit of TL0. The higher 1-bit of TH0 and higher 3-bit of TL0 are disregarded. When this 12-bit register is overflowed, set TF0 to ‘1’. The operation of timer1 is same as that of timer0. Rev A ZIC2410 Datasheet Descriptions Document No. 0005-05-07-00-000 Reset ...
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... TL0 controls as the control signals of Timer0. TH0 is always used as a timer function and it controls as TR1 of Timer1. The overflow is stored in TF1. At this time, Timer1 is disabled and it retains the previous value. Rev A ZIC2410 Datasheet Figure 12 – Timer0 Mode0 Figure 13 – Timer0 Mode1 Figure 14 – Timer0 Mode2 Document No ...
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... If the time-out period is set too short, excessive interrupts will occur causing abnormal operation of the system recommended to set a sufficient time-out period for Timer2 (> 100µs). Timer3 acts as a general 16-bit timer. Time-out period of Timer3 is calculated by Equation 2. Equation 2 – Time-out Period Calculation (Timer3) Rev A ZIC2410 Datasheet C/T C TL0 ...
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... Table 13 – Frequency and Duty Rate in PWM Mode Channel PWM2 PWM3 Note: This equation does not apply for TH values of 0, and 1. For these values the frequency should be as follows: TH=0: 15.625 KHz; TH=1: 7.812 KHz. Rev A ZIC2410 Datasheet × × 256 ...
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... Reset interval of WDT is calculated by the Equation 3. For example, when WDTPRE value is ‘0’ and system clock of MCU is 8MHz, reset interval of WDT is 65.536ms. Equation 3 – Watchdog Reset Interval Calculation Watchdog Reset Interval = Rev A ZIC2410 Datasheet Table 14 – Watchdog Timer Register Descriptions × 256 ...
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... Table 16 – Sleep Timer Delay Registers Bit Name Delay Time = RTDLY × 32.768KHz when ST clock source is 7:0 RTDLY 32.768KHz. The value of RTDLY should be greater than 2. Rev A ZIC2410 Datasheet Table 15 – Sleep Timer Registers Descriptions Descriptions Document No. 0005-05-07-00-000 Reset R/W Value R/W ...
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... MCU. The Internal RC oscillator can be controlled by the 3 PDCON (0x22F1) register. When this bit is set to ‘1’, internal RC Oscillator is enabled. The default value is ‘1’. Figure 16 – Selecting the Clock Oscillator Rev A ZIC2410 Datasheet Document No. 0005-05-07-00-000 rd bit in the Page 33 of 119 ...
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... Shows whether the interrupt is pending or not. When this field is 0 PENDING ‘0’, the interrupt is pending. Note: IIR register uses the same address as FCR register in Table 19 below. IIR register is read-only and FCR register is write-only. Rev A ZIC2410 Datasheet Table 17 – UART0 Registers Descriptions 18 . Document No. 0005-05-07-00-000 Reset ...
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... In reception PEN mode, checks parity. When this field is ‘0’, parity is not generated. Rev A ZIC2410 Datasheet Table 18 – UART0 Interrupt Lists Interrupt Source Parity, Overrun or Framing errors or Break Interrupt FIFO trigger level reached ...
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... Shows whether the interrupt is pending or not. When this field is ‘0’, 0 PENDING the interrupt is pending. Note: IIR register uses the same address as FCR register in Table 22 below. IIR register is read-only and FCR register is write-only. Rev A ZIC2410 Datasheet Descriptions Table 20 – UART1 Registers Descriptions Table 21 – UART1 Interrupt Lists Document No. 0005-05-07-00-000 Reset ...
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... Number of Stop Bits. When this field is set to ‘1’, 2 stop bit is 2 used. When transmitting a word (character bit length, 1.5 stop STB bit is used. When this field is ‘0’, 1 stop bit is used. Rev A ZIC2410 Datasheet Interrupt Source Parity, Overrun or Framing errors or Break Interrupt FIFO trigger level reached There is at least 1 character in ...
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... Modem Status Register and the Port Enable Register in the UART1 block. This document doesn’t include these registers because they are not used commonly. For more detailed information on their use, please contact CEL. Rev A ZIC2410 Datasheet Descriptions Document No. 0005-05-07-00-000 Reset R/W ...
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... SPI Clock Rate Select. With ESPR field in SPER register 1:0 (0x2543), selects SPI clock (SCK) rate when the device is SPR configured as a Master. Refer to the ESPR field in Table 25. Rev A ZIC2410 Datasheet Figure 17 – SPI Data Transfer Table 23 – SPI Control Registers Descriptions Document No. 0005-05-07-00-000 Reset ...
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... SPSR (SPI STATUS REGISTER, 0x2541) SPI Interrupt Flag: When SPI interrupt occurs, this field is set to 7 ‘1’. Set whenever data transmission is finished and it can be SPIF cleared by software. Rev A ZIC2410 Datasheet SCK when idle Low Low High High Figure 18 – (a) CPOL=0, CPHA=0 Figure 19 – ...
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... ESPR field : high bit SPR field: low bit The value of ESPR and SPR is used to divide system clock to generate SPI clock (SCK). For example, if the value of ESPR and SPR is ‘0010’ and system clock is 8MHz, SPI clock (SCK) is 1MHz. Rev A ZIC2410 Datasheet Descriptions (System Clock Divider) 0000 0001 ...
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... Voice FIFO DMA The data generated through an external ADC is input to the voice block in the ZIC2410 via an I2S interface. Data received via I2S is compressed at the voice codec, and stored in the Voice TXFIFO. The data is then transferred to the MAC TX FIFO through DMA operation and finally transmitted through the PHY layer ...
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... Other fields are set to ‘0’. In ISP mode, BPOL field in STXMODE (0x252D) register is set to ‘0’. In other modes, BPOL field in STXMODE (0x252D) register is set to ‘0’ or ‘1’ respectively. Rev A ZIC2410 Datasheet Figure 22 – (a) I2S Mode Figure 23 – (b) Left Justified Mode Figure 24 – (c) Right Justified Mode Figure 25 – ...
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... I2S RX block is input to the LRCK of the I2S TX block. Ddetermines the polarity of MCLK. When this field is ‘0’, MCLK 6 MPOL signal retains ‘1’. When this field is ‘1’, MCLK signal retains ‘0’. Rev A ZIC2410 Datasheet Table 26 – I2S Registers Descriptions × STXSDIV) Document No. 0005-05-07-00-000 ...
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... Sets the value for dividing a system clock to generate MCLK. The equation is as follows: 7:0 SRXSDIV MCLK = System Clock/(2 When this field is ‘0’, MCLK is not generated. SRXMDIV (I2S RX MCLK DIVISOR REGISTER, 0x253B) Rev A ZIC2410 Datasheet Descriptions × SRXSDIV) Document No. 0005-05-07-00-000 Reset R/W Value ...
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... MLT Mode. Only the data in Left channel is transferred.(‘0’ is transferred in Right channel) 3: STR Mode. All data in Left or Right channel are transferred. 0 Clock Enable. When this field is set to ‘1’, I2S RX is enabled. CLKENA 1.7.8.2 VOICE CODEC ZIC2410 includes three voice codec algorithms. • µ-law • a-law • ADPCM The µ ...
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... SEL 2: a-law 3: ADPCM When this field is set to ‘1’, the pointer in voice decoder is 1 INI initialized. This field cannot be read. 0 ENA Decoder Enable. Rev A ZIC2410 Datasheet Table 27 – VODEC Registers Descriptions Document No. 0005-05-07-00-000 Reset R/W Value R/W 0 R/W 0 R/W ...
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... Set to ‘1’ while popping data on Voice TX FIFO. POP 1:0 Reserved VTDSIZE (VOICE TX DMA SIZE REGISTER (VOICE TX FIFO->MAC TX FIFO), 0x275B) 7:0 Set the data size for DMA operation. VTDSIZE Rev A ZIC2410 Datasheet Descriptions Table 28 – Voice TX Registers Descriptions Document No. 0005-05-07-00-000 Reset R/W Value Reset ...
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... Set to ‘1’ while popping data on the Voice RX FIFO. POP 1:0 Reserved VRDSIZE (VOICE RX DMA SIZE REGISTER (MAC RX FIFO->VOICE RX FIFO), 0x276B) 7:0 Sets the data size for DMA. VRDSIZE Rev A ZIC2410 Datasheet Table 29– Voice RX Registers Descriptions Document No. 0005-05-07-00-000 Reset R/W Value R/W 0x00 ...
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... DECB16 When this field is set to ‘1’, high 8-bit data of 16-bit data is transferred first and then low 8-bit data is transferred. 3 Reserved Rev A ZIC2410 Datasheet Table 30– Voice Interrupt Registers Descriptions Document No. 0005-05-07-00-000 Reset R/W Value R/W ...
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... RNGC (RNG DATA3 REGISTER, 0x2558) 7:1 Reserved RNG Enable. When this field is set to ‘1’, RNG acts. This field 0 ENA value is changed to ‘0’ automatically. Rev A ZIC2410 Datasheet Descriptions Descriptions nd MSB (RNG [23:16]) of 32-bit random rd MSB (RNG [15:8]) of 32-bit random number. rd MSB (SEED [15:8]) of required seed to Document No ...
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... Drawing (b) shows that the XB signal is changing before the XA signal. In this case, the pointing device is moving in the up direction. The rules for YA, YB, ZA and ZB are the same as described above for XA and XB. Figure 26 – Quadrature Signal Timing between XA and XB. Rev A ZIC2410 Datasheet (a) (b) Document No. 0005-05-07-00-000 Page 52 of 119 ...
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... INTERNAL VOLTAGE REGULATOR There are separate Analog and Digital regulators in the ZIC2410. The Analog regulator supplies power to the RF and analog blocks, while the Digital regulator supplies power to all the digital blocks. MSV, an external pin, sets the output voltage: when MSV is set to ‘0’, 1.5V is generated and when MSV is set to ‘ ...
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... SADCVALH (SENSOR ADC OUTPUT VALUE HIGH DATA REGISTER, 0x22AC) This register stores the output value of sensor ADC (SADCVAL). SADCVAL, which is a 15bit unsigned integer value, is stored in the SADCVALH and SADCVALL register. SADCVALH stores 8 bit MSB of SADCVAL (SADCVAL [14:7]). Rev A ZIC2410 Datasheet Table 33– Sensor ADC Registers Descriptions Reference Description TOP = 1 ...
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... ONCHIP POWERON RESET This block generates the reset signal to initialize the digital block during power-up. When On- chip regulator output or external battery is used as the power of digital core block and power is provided, it outputs the internal reset signal. Rev A ZIC2410 Datasheet Descriptions Document No. 0005-05-07-00-000 Reset R/W ...
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... To control the functionality of this block, refer to the section 1.7.12. Whenever temperature is increased by 1°C, the output of this block is decreased by -16.5mV/°C. Figure 27 below graphs the typical output value vs. the temperature sensed. Improved accuracy can be achieved through calibration. Figure 27 – Typical Temperature Sensor Characteristics Rev A ZIC2410 Datasheet Document No. 0005-05-07-00-000 Page 56 of 119 ...
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... This block can be used to monitor the voltage level of the 3V supply. To control the functionality of this block, refer to the section 1.7.12. Figure 28 below graphs the output value of the monitor vs. the input voltage. Figure 28 – Battery Monitor Characteristics Rev A ZIC2410 Datasheet Document No. 0005-05-07-00-000 Page 57 of 119 ...
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... MAC header. The FCS field is defined as the MAC footer. The data which is transmitted from the higher layer is located in the MAC payload. For detailed information on frame format, refer to the IEEE802.15.4 standard. Rev A ZIC2410 Datasheet Figure 29 – MAC block diagram Document No. 0005-05-07-00-000 Page 58 of 119 ...
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... Pointer and a Read Pointer. The RX FIFO can store several frame data received from the PHY block. Since the LSB of each frame data represents the frame data length, it can be accessed by the Write pointer and the Read Pointer. Rev A ZIC2410 Datasheet x16 + x12 + Document No. 0005-05-07-00-000 Page 59 of 119 ...
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... In order to implement CCM* mode by ZigBee and CTR/CBC-MAC/CCM mode by IEEE 802.15.4, a 128-bit key value and a nonce are needed. ZIC2410 can have two 128-bit key values, KEY0 and KEY1. For encryption, the desired nonce value should be stored in the TX Nonce and KEY0 or KEY1 should be selected for use. For decryption, the desired nonce value should be stored in the RX Nonce and KEY0 or KEY1 should be selected for use ...
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... TX FIFO. This field is set by the MCU or is set MTFCSLE 7:0 automatically to the length of a packet to be transmitted when the N ASA field in the MTFCCTL register is set to ‘1’. Rev A ZIC2410 Datasheet Table 34 – MAC TX FIFO Registers Descriptions Document No. 0005-05-07-00-000 Reset R/W Value ...
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... RX FIFO. This field is set by the MCU or is set MRFCSLE 7:0 automatically to the length of the received packet when the ASA N field in the MRFCCTL register is set to ‘1’. Rev A ZIC2410 Datasheet Table 35 – MAC RX FIFO Registers Descriptions Document No. 0005-05-07-00-000 Reset R/W Value ...
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... PAN ID [15:8] PANID 0x2158: the PAN ID [7:0] SHORTADDR (SHORTADDRESS REGISTERS, 0x215A~0x215B) Stores the Short address (Network address). SHORTAD 7:0 0x215B : Short address [15:8] DR 0x215A : Short address [7:0] Rev A ZIC2410 Datasheet Descriptions Document No. 0005-05-07-00-000 Reset R/W Value R/W 0x00 R/W 0x00 R/W ...
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... Sets the DSN field value of the received ACK packet, which can 7:0 cause a PHY (RX) interrupt. In other words, if the DSN field of the MACDSN received ACK packet is not equal to MACDSN, the PHY (RX) interrupt does not occur. Rev A ZIC2410 Datasheet Document No. 0005-05-07-00-000 R/O 0 R/O 0 R/O ...
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... FIFO. RXAL Security mode: CBC-MAC – It represents the number of bytes between length byte and the data to be authenticated. Security mode: CCM – It represents the length of the data which is used not in encoding or decoding but in authentication. Rev A ZIC2410 Datasheet Authentication Field Length Reserved ...
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... Symbol-to-Chip mapping is used for spreading the symbol bandwidth to improve the reception performance. Table 37 shows the mapping rule of chip sequences corresponding to each symbol. Table 37 – Spreading sequence of 32-chip Symbol Rev A ZIC2410 Datasheet Figure 31 – IEEE 802.15.4 Modulation Chip Sequence ( … Document No. 0005-05-07-00-000 ) 31 Page 66 of 119 ...
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... Clear Channel Assessment (CCA) operation is based on this information. The CCA operation is used to prevent a collision when multiple-users try to use a channel simultaneously. When a channel is determined to be busy, packet transmission is deferred until the channel state changes to idle. Rev A ZIC2410 Datasheet Document No. 0005-05-07-00-000 Page 67 of 119 ...
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... CEL, and should not be modified by a user’s application program. Table 38 lists the registers in the PHY Layer of the ZIC2410. The address of each register is assigned to a data memory area in the microcontroller user application program can read and write the register as a general memory. Table 38 – ...
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... PLL3 2289 PLL4 228A PLL5 22A0 TXPA0 22A1 TXPA1 22A2 TXPA2 Rev A ZIC2410 Datasheet Description RF TX Path Power-Down RF TX Path Power-Up TRSWB Control RX Frame Format1 SYNC Word Register Operation Delay Control 0 Operation Delay Control 1 TX Frame Format1 AGC Configuration3 CCA Control0 ...
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... OFF. In the OFF state, the RF block power- down state and the modem block is in the reset state. In this state, the 7 ZIC2410 cannot receive or transmit packets. For transmission or MDOFF reception of a packet, the modem block needs to be changed to the ON state. When the modem block goes to the OFF state, this field is set to ‘ ...
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... The following table shows the VCO buffer VCOBP 3 circuit state based on the values of the VCOBPD and VCOBPU fields. D VCOBPD Rev A ZIC2410 Datasheet Descriptions Always enabled Always enabled Always disabled Enabled or disabled depending on the control of a modem block PLLRSTC PLL reset state 1 Controlled by the modem block ...
Page 72
... Divider circuit is enabled. When the DIVPU field 1 DIVPU is set to ‘0’, the Divider circuit is in the power-up state. See DIVPD above for the truth table. Rev A ZIC2410 Datasheet Descriptions VCO state 1 Controlled by the modem block 0 Always power-up state. ...
Page 73
... RX Mixer Buffer circuit state based on the values of the RMIXB 4 RMIXBUFPD and RMIXBUFPU fields. UFPD RMIXBUFPD Reserved and should be fixed to ‘0’. Rev A ZIC2410 Datasheet Descriptions LNA state 1 Controlled by the modem block 0 Always power-up state. 1 Always power-down state 0 Always power-up state. RMIXPU RX Mixer state ...
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... RX Mixer Buffer circuit. In the power-up state, the RX Mixer Buffer RMIXB 4 circuit is enabled. When the RXMIXBUFPU field is set to ‘0’, the RX UFPU Mixer Buffer circuit is in the power-up state. See RXMIXBUFPD above for truth table. Rev A ZIC2410 Datasheet Descriptions RLPFPU RX LPF state 1 Controlled by the modem block 0 Always power-up state. ...
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... TX Up-mixer circuit state based on the values of the TXUMPD and TXUMP 2:1 TXUMPU fields. The values of ‘1’ and ‘2’ are not used in these fields. D TXUMPD Rev A ZIC2410 Datasheet Descriptions TXUMBUFPU TX Up-mixer Buffer state 1 Controlled by the modem block 0 Always power-up state. 1 Always power-down state. 0 Always power-up state ...
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... Supports 250kbps data rate (compatible with IEEE802.15.4 std Supports 250kbps and 500kbps data rates Supports 250kbps and 1Mbps data rates Transmission Rate. Sets the transmisson data rate. ZIC2410 supports 250kbps compatible with IEEE802.15.4 standard and 500kbps or 1Mbps extended data rate provided by CEL Inc. TXRAT 5:4 0: Supports 250kbps data rate (compatible with IEEE802 ...
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... Reserved TX Packet Preamble Length. Sets the preamble length of the transmission packet. The ZIC2410 supports a preamble of 8 symbol length defined in the IEEE 802.15.4 std. At the same time, the ZIC2410 provides a configurable preamble length. When ‘n’ value is set in TXPRM 3:0 TXPRMLNG field, the length of the preamble is set to (n+6)symbol. The LNG length of preamble can be varied from symbols ...
Page 78
... CCATHRS register is 0xB2 and corresponds to ‘-78dBm’. CCA2 (CCA CONTROL CONFIGURATION2 REGISTER) R/W. Energy Calculation Offset(ENRGOFST) The ZIC2410 and calculates the energy level of the received signal based on the gain of RF block per the following equation. Equation 4 – Calculation of RX Signal Energy Level Energy Level (dBm) = CCA2 – ...
Page 79
... The small change in energy level may cause some uncertainty in determining the channel state when that state is defined using only the threshold of the CCA1 register. To prevent that uncertainty, the ZIC2410 can define a hysteresis value to define a minimum drop in energy level to initiate a change in the channel state from busy to the idle state. The CCA3 register is used to set that hysteresis ...
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... TST14 register can set from a 1/4 frequency of DAC operating clock to a 1/256 frequency of DAC operating clock. This single-tone signal can be used to test RF block characteristics. Cosine and sine signal can be selectively assigned to I-phase or Q-phase of RF block. The frequency of single-tone is defined by Equation 5. Rev A ZIC2410 Datasheet Table 41 – Test Mode Setting TSTMD [4] [3:2] ...
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... In order to be changed to the recorded state, TXSTS TXSTSF field should be set to ‘0’. The state in TXSTS field can be different from the recorded state because TXSTS shows the current state of modulation block. The following table shows the state in TXSTS. Rev A ZIC2410 Datasheet ⋅ f CFRQ Frequency = DAC Hz 1024 Table 43 – ...
Page 82
... The state in MDSTS field can be different from the recorded state because MDSTS shows the current state of the modem block. Table shows the state in MDSTS. Rev A ZIC2410 Datasheet Descriptions TX_IDLE: The modulation block cannot transmit a packet. TX_WAIT1: The modulation block is waiting for the TX FIFO to be ready before packet transmission ...
Page 83
... The RX Mixer gain with MG=’1’ higher than with MG=’0’. When MG the value of the MGF field is ‘0’, the MG field sets the gain of RX Mixer. Rev A ZIC2410 Datasheet Table 44 – MDSTS Field Table 45 – AGC Status Registers Descriptions Document No. 0005-05-07-00-000 state ...
Page 84
... AGCSTS3 register shows the energy level of the last received packet. The value in AGCSTS3 register is retained until another packet is received. Rev A ZIC2410 Datasheet Stage 1 gain (0 ~ 3dB) ‘00’ : 0dB ‘01’ : 1dB ‘ ...
Page 85
... This register is used to indicate the kinds of the interrupt when the multiple interrupts occur. 7:5 Reserved Reception of Extended Transfer Rate Packet. This field is equal to 4 FRMDX the FRMDX field in the INTIDX register. Rev A ZIC2410 Datasheet Descriptions Interrupt MDREADY_INT interrupt TXEND_INT interrupt RXSTART_INT interrupt RXEND_INT interrupt Document No. 0005-05-07-00-000 ...
Page 86
... TRSWB, the complementary signal of TRSW, remains as a logic ‘0’ during packet transmission and as a logic ‘1’ during packet reception. TRSWC1 register should be set to ‘0x00’ to output TRSW and TRSWB signal. Rev A ZIC2410 Datasheet Descriptions Document No. 0005-05-07-00-000 Reset R/W ...
Page 87
... To change the channel setting, the PLL0, PLL1, PLL2, PLL3, PLL4 registers need to be changed by the following procedure: 1) Change the RF RX-path to the power-down state by setting the RXRFPD register to 00000000. Rev A ZIC2410 Datasheet Table 47 – FRAC_K[19:0] Registers PLL0 PLL1 Address: 0x2286 Address: 0x2287 ...
Page 88
... In-system programming (ISP) function enables a user to download an application program to the internal flash memory. When Power-on, the ZIC2410 checks the value of the MS [2:0] pin. When the value of the MS [2] pin is ‘1’ and the value of the MS [1:0] is ‘0’, ISP mode is selected. ...
Page 89
... CLR A Clear Accumulator CPL A Complement Accumulator RL A Rotate Accumulator Left RLC A Rotate Accumulator Left through the Carry RR A Rotate Accumulator Right RRC A Rotate Accumulator Right through the Carry Rev A ZIC2410 Datasheet Table 50 – Instruction Set Summary DESCRIPTION Document No. 0005-05-07-00-000 BYTE CYCLE ...
Page 90
... Jump if direct Bit is set JNB bit,rel Jump if direct Bit is Not set JBC bit,rel Jump if direct Bit is set & clear bit PROGRAM BRANCHING ACALL addr11 Absolute Subroutine Call LCALL addr16 Long Subroutine Call RET Return from Subroutine Rev A ZIC2410 Datasheet DESCRIPTION Document No. 0005-05-07-00-000 BYTE CYCLE ...
Page 91
... Compare immediate to register and Jump if Not Equal CJNE @Ri,#data,rel Compare immediate to indirect and Jump if Not Equal DJNZ Rn,rel Decrement register and Jump if Not Zero DJNZ direct,rel Decrement direct byte and Jump if Not Zero NOP No Operation Rev A ZIC2410 Datasheet DESCRIPTION Document No. 0005-05-07-00-000 BYTE CYCLE ...
Page 92
... DIGITAL I/O EQUIVALENT SCHEMATIC RESET# XOSCI/XOSCO, RTCI/RTCO GPIO (P0, P1, P3) MS2,MS1, MS0,MSV TSRW, CSROM# Rev A ZIC2410 Datasheet POWER (uW/MHz) 4.67 53.86 82.08 3.53 55.67 Document No. 0005-05-07-00-000 MAX DRIVE (mA) N.A N.A 4 N.A. 4 Page 92 of 119 ...
Page 93
... AC & DC CHARACTERISTICS 2.1 ABSOLUTE MAXIMUM RATINGS Table 51 – Absolute Maximum Ratings: ZIC2410 (all packages) Symbol Parameter VDD Chip Core Supply Voltage VDDIO I/O Supply Voltage RFIN Input RF Level TSTG Storage Temperature Exceeding one or more of these ratings may cause permanent damage to the device. ...
Page 94
... Premium Mode (1Mbps) 1 AVDD_VCO, AVDD_RF1, AVDD_CP, AVDD_DAC, AVDD, DVDD_XOSC, DVDD 2 Refer to Section 1.4 in this document for register setting of MCU clock. 3 Based on the Teradyne J750 MP(Mass Production) test equipment 4 ZigBee Standard Rev A ZIC2410 Datasheet 1 =1.5V, MCU Clock=8MHz ZIC2410QN48 min typ 3.35 43 41.4 39.8 37 ...
Page 95
... PLL Lock Time PLL Jitter Crystal Oscillator Frequency Crystal Frequency Accuracy Requirement On-chip RC Oscillator Frequency Sensor ADC Number of Bits Rev A ZIC2410 Datasheet 1 2 =1.5V, MCU Clock=8MHz ZIC2410QN48 min typ max –9.6 – ...
Page 96
... Voltage Regulator Input Voltage=3V, 80mV voltage drop 6 Voltage Regulator Input Voltage=3V, 80mV voltage drop 7 μ and 100pF load capacitor 8 μ and 100pF load capacitor Rev A ZIC2410 Datasheet 1 2 =1.5V, MCU Clock=8MHz ZIC2410QN48 min typ max 256 ±1.7 ±2.4 51.0 1.9 3.0 3 ...
Page 97
... Refer to Section 1.4 in this document for register setting of MCU clock. 11 Based on the Teradyne J750 MP(Mass Production) test equipment 12 Based on the Teradyne J750 MP(Mass Production) test equipment 13 ZigBee Standard Rev A ZIC2410 Datasheet 9 =1.5V, MCU Clock=16MHz ZIC2410QN48 min typ 4.6 46.3 44.6 43.0 43 ...
Page 98
... PLL Lock Time PLL Jitter Crystal Oscillator Frequency Crystal Frequency Accuracy Requirement On-chip RC Oscillator Frequency Sensor ADC Number of Bits Conversion Time Rev A ZIC2410 Datasheet 9 10 =1.5V, MCU Clock=16MHz ZIC2410QN48 min typ max –9.6 – ...
Page 99
... VALID 14 Voltage Regulator Input Voltage=3V, 80mV voltage drop 15 Voltage Regulator Input Voltage=3V, 80mV voltage drop 16 μ and 100pF load capacitor 17 μ and 100pF load capacitor Rev A ZIC2410 Datasheet 9 =1.5V, MCU Clock=16MHz ZIC2410QN48 min typ ±1.7 ±2.4 51.0 1.9 3.0 1 260 Table 55 – Timing Specifications ...
Page 100
... Rev A ZIC2410 Datasheet Figure 34 – POR Timing Figure 35 – RESET# Timing Figure 36 – GPIO Timing Document No. 0005-05-07-00-000 Page 100 of 119 ...
Page 101
... PACKAGE & PIN DESCRIPTIONS 3.1 PIN ASSIGNMENTS 3.1.1 QN48 Package Figure 37 – Pin-out top view of QN48 Package * Chip Ground (GND) is located in the center on the bottom of a chip. Rev A ZIC2410 Datasheet Document No. 0005-05-07-00-000 Page 101 of 119 ...
Page 102
... The ZIC2410QN48 Pin-out overview is shown in Table 56. Table 56 – Pin-out overview; QN48 package Pin NO. Pin Name Pin Type Exposed GND Ground bottom 1 AVDD_VCO Power 2 AVDD_RF1 Power 3 RF_N 4 RF_P 5 RBIAS Analog Power 6 AVDD (In/Out) 7 AVREG3V Power 8 ACH0 Analog 9 ACH1 Analog 10 ACH2 Analog 11 ACH3 ...
Page 103
... XOSCI Analog 47 DVDD_XOSC Power 48 AVDD_CP Power Rev A ZIC2410 Datasheet Pin Description Port P3.2 / INT0 (active low) Port P3.1 / TXD0 / QUADXB 3.0V Power supply for Digital IO Port P3.0 / RXD0 / QUADXA Port P0.7 / I2STX_MCLK Port P0.6 / I2STX_BCLK Port P0.5 / I2STX_LRCLK Port P0.4 / I2STX_DO Port P0 ...
Page 104
... FG72 Package Figure 38 – Pin-out top view (1) of ZIC2410FG72 (72-pin VFBGA Package) Figure 39 – Pin-out top view (2) of ZIC2410FG72 (72-pin VFBGA Package) Rev A ZIC2410 Datasheet Document No. 0005-05-07-00-000 Page 104 of 119 ...
Page 105
... The ZIC2410FG72 Pin-out overview is shown in Table 57. Ball Ball Name Ball Type A1 AGND Ground A2 AVDD_VCO Power A3 AGND Ground A4 DGND Ground A5 XOSCI Analog A6 XOSCO Analog A7 P0[0] I/O(digital) A8 P0[5] I/O(digital) A9 P0[6] I/O(digital) B1 AVDD_RF1 Power B2 AVDD_CP Power B3 AGND Ground B4 DGND Ground B5 DVDD_XOSC Power B6 B7 P0[2] ...
Page 106
... Ground for RF and Analog blocks. MS[2:0](Mode Select): ▪ When using Internal Regulator of ZIC2410 000: Normal mode 100: ISP mode ▪ When NOT using Internal Regulator of ZIC2410 010:Normal mode 110: ISP mode Mode Select of Voltage. 0:1.5V 3.0V Power supply for Internal Voltage Regulator. ...
Page 107
... PACKAGE INFORMATION 3.2.1 PACKAGE INFORMATION: ZIC2410QN48 (QN48pkg) Package is 48-pin QFN type package with down-bonding. Rev A ZIC2410 Datasheet Document No. 0005-05-07-00-000 Page 107 of 119 ...
Page 108
... Rev A ZIC2410 Datasheet MAX NOTES 0.90 1. Dimensions and Tolerances conform to ASME Y14.5N-1994 0.05 2. All Dimensions are in millimeters; all angles are in degrees 0.30 3. Dimension “b” applies to metalized terminals and is measured between 0.25 and 0.30mm from the terminal tip ...
Page 109
... Figure 41 – QN48 Carrier Tape & Reel Specification Rev A ZIC2410 Datasheet Document No. 0005-05-07-00-000 Page 109 of 119 ...
Page 110
... PACKAGE INFORMATION: ZIC2410FG72 (FG72pkg) Package type is 72-pin VFBGA package with ball-bonding. Rev A ZIC2410 Datasheet Figure 42 – FG72 Package Drawing Document No. 0005-05-07-00-000 Page 110 of 119 ...
Page 111
... Figure 43 – FG72 Carrier Tape & Reel Specification Rev A ZIC2410 Datasheet g) Document No. 0005-05-07-00-000 Page 111 of 119 ...
Page 112
... APPLICATION CIRCUITS 3.3.1 APPLICATION CIRCUITS (QN48 package) The ZIC2410 operates from a single supply voltage. The core must run at 1.5V, so, if 1.5V is available, both the core and the I/O can run from 1.5V higher voltage I/O is required (or higher voltage is available on the board) the ZIC2410 contains an on-chip voltage regulator that can step down a 1 ...
Page 113
... Figure 45 shows the application circuit of the ZIC2410QN48 when using 1.5V as the I/O power and not using the internal regulator. In this case, a software setting is needed to turn off the internal regulator of the device. *** GND is bottom pad (down-bonding pad) in the above schematic Figure 45 – the ZIC2410QN48 Application Circuit (I/O Power: 1.5V , MS[1]=1) NOTE: When the ZIC2410 is operated below minimum operating voltage, a reset error will occur because of the unstable voltage ...
Page 114
... APPLICATION CIRCUITS (FG72 package) The ZIC2410 operates from a single supply voltage. The core must run at 1.5V, so, if 1.5V is available, both the core and the I/O can run from 1.5V higher voltage I/O is required (or higher voltage is available on the board) the ZIC2410 contains an on-chip voltage regulator that can step down a 1 ...
Page 115
... Figure 47 shows the application circuit of the ZIC2410FG72 when using 1.5V as the I/O power and not using the internal regulator. In this case, a software setting is needed to turn off the internal regulator of the device. Figure 47 – ZIC2410FG72 Application Circuit (I/O Voltage: 1.5V , MS[1]=1) NOTE: When the ZIC2410 is operated below minimum operating voltage, a reset error will occur because of the unstable voltage. For more detailed information, refer to the Note of ‘ ...
Page 116
... TABLE 28 – VOICE TX REGISTERS ......................................................................................................... 48 TABLE 29– VOICE RX REGISTERS .......................................................................................................... 49 TABLE 30– VOICE INTERRUPT REGISTERS .......................................................................................... 50 TABLE 31– RANDOM NUMBER GENERATOR REGISTERS .................................................................. 51 TABLE 32– POINTER AND QUAD CONTROL REGISTERS .................................................................... 53 TABLE 33– SENSOR ADC REGISTERS ................................................................................................... 54 Rev A ZIC2410 Datasheet Document No. 0005-05-07-00-000 ...
Page 117
... TABLE 48 – PHASE LOCK LOOP CONTROL REGISTERS ..................................................................... 87 TABLE 49 – TX OUTPUT POWER SETTINGS .......................................................................................... 88 TABLE 50 – INSTRUCTION SET SUMMARY ............................................................................................ 89 TABLE 51 – ABSOLUTE MAXIMUM RATINGS: ZIC2410 (ALL PACKAGES) .......................................... 93 TABLE 52 – DC CHARACTERISTICS: ZIC2410 (ALL PACKAGES) ......................................................... 93 TABLE 53 – ELECTRICAL SPECIFICATIONS: 8MHZ CLOCK ................................................................. 94 TABLE 54 – ELECTRICAL SPECIFICATIONS: 16MHZ CLOCK ............................................................... 97 TABLE 55 – ...
Page 118
... FIGURE 43 – FG72 CARRIER TAPE & REEL SPECIFICATION ............................................................ 111 FIGURE 44 – ZIC2410QN48 TYPICAL APPLICATION CIRCUIT (I/O POWER: 1.9V~3.3V , MS[1]=0) . 112 FIGURE 45 – THE ZIC2410QN48 APPLICATION CIRCUIT (I/O POWER: 1.5V , MS[1]=1) ................... 113 FIGURE 46 – ZIC2410FG72 APPLICATION CIRCUIT (I/O VOLTAGE: 1.9V~3.3V , MS[1]=0) .............. 114 ...
Page 119
... FIGURE 47 – ZIC2410FG72 APPLICATION CIRCUIT (I/O VOLTAGE: 1.5V , MS[1]=1) ........................ 115 4.3 TABLE OF EQUATIONS EQUATION 1 – TIME-OUT PERIOD CALCULATION (TIMER2) ............................................................... 29 EQUATION 2 – TIME-OUT PERIOD CALCULATION (TIMER3) ............................................................... 29 EQUATION 3 – WATCHDOG RESET INTERVAL CALCULATION ........................................................... 31 EQUATION 4 – CALCULATION OF RX SIGNAL ENERGY LEVEL .......................................................... 78 EQUATION 5 – DEFINITION OF SINGLE-TONE FREQUENCY ............................................................... 81 5 REVISION ...