MAX9930EVKIT+ Maxim Integrated Products, MAX9930EVKIT+ Datasheet - Page 14

• Manufacturer Part Number: MAX9930EVKIT+
• Description: RF Modules & Development Tools KIT EVAL FOR MAX9930 MAX9930 KIT
• Manufacturer: Maxim Integrated Products

Specifications of MAX9930EVKIT+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX9930–MAX9933 family of logarithmic amplifiers
respond to voltage, not power, even though input levels
are specified in dBm. It is important to realize that input
signals with identical RMS power but unique waveforms
result in different log amp outputs. Differing signal wave-
forms result in either an upward or downward shift in the
logarithmic intercept. However, the logarithmic slope
remains the same; it is possible to compensate for known
waveform shapes by baseband process.
It must also be noted that the output waveform is generat-
ed by first rectifying and then averaging the input signal.
This method should not be confused with RMS or peak-
detection methods.
As with any RF circuit, the layout of the MAX9930–
MAX9933 circuits affects performance. Use a short 50Ω
line at the input with multiple ground vias along the
length of the line. The input capacitor and resistor
should both be placed as close as possible to the IC.
V
with multiple vias connecting the capacitor to the
ground plane. It is recommended that good RF compo-
nents be chosen for the desired operating frequency
range. Electrically isolate RF input from other pins
(especially SET) to maximize performance at high
frequencies (especially at the high power levels of
the MAX9932).
2MHz to 1.6GHz 45dB RF-Detecting
Controllers and RF Detector
PROCESS: High-Frequency Bipolar
14
CC
should be bypassed as close as possible to the IC
______________________________________________________________________________________
Waveform Considerations
Layout Considerations
Chip Information
SHDN
SHDN
RFIN
RFIN
*INVERTING VOLTAGE TO CURRENT CONVERTER.
V
V
SET
CC
CC
GND
GND
MAX9930
MAX9931
MAX9932
MAX9933
DETECTOR
DETECTOR
LOG
LOG
V-I*
BLOCK
BLOCK
g
m
g
m
V-I*
Block Diagram
OUTPUT-
ENABLE
DELAY
OUTPUT-
ENABLE
DELAY
BUFFER
BUFFER
x1
x1
OUT
C
OUT
C
CLPF
CLPF