EZLC-4421 HB Silicon Laboratories Inc, EZLC-4421 HB Datasheet - Page 30

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EZLC-4421 HB

Manufacturer Part Number
EZLC-4421 HB
Description
Wireless Accessories EZLink Fast Prototype Kit Hiband
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of EZLC-4421 HB

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Typical TX register usage
Note: The content of the data registers are initialized by clearing bit et.
A complete transmit sequence should be performed as follows:
It is possible to perform this sequence without sending a dummy byte (step i.) but after loading the last data byte to the transmit
register the PA turn off should be delayed for at least 16 bits time. The clock source of the microcontroller (if the clock is not supplied
by the Si4421) should be stable enough over temperature and voltage to ensure this minimum delay under all operating
circumstances.
When the dummy byte is used, the whole process is driven by interrupts. Changing the TX data rate has no effect on the algorithm
and no accurate delay measurement is needed.
a.
b.
c.
d.
e.
f.
g.
h.
i.
j.
k.
l.
Enable the TX register by setting the el bit to 1 (Configuration Setting Command, page 15)
The TX register automatically filled out with 0xAAAA, which can be used to generate preamble.
Enable the transmitter by setting the et bit (Power Management Command, page 15)
The synthesizer and the PLL turns on, calibrates itself then the power amplifier automatically enabled
The TX data transmission starts
When the transmission of the byte completed, the nIRQ pin goes high, the SDO pin goes low at the same time. The nIRQ
pulse shows that the first 8 bits (the first byte, by default 0xAA) has transmitted. There are still 8 bits in the transmit
register.
The microcontroller recognizes the interrupt and writes a data byte to the TX register
Repeat f. - g. until the last data byte reached
Using the same method, transmit a dummy byte. The value of this dummy byte can be anything.
The next high to low transition on the nIRQ line (or low to high on the SDO pin) shows that the transmission of the data
bytes ended. The dummy byte is still in the TX latch.
Turn off the transmitter by setting the et bit to 0. This event will probably happen while the dummy byte is being
transmitted. Since the dummy byte contains no useful information, this corruption will cause no problems.
Clearing the el bit clears the Register Underrun interrupt; the nIRQ pin goes high, the SDO low.
(enable transmitter)
Synthesizer / PA
SPI commands
(nSEL, SCK, SDI)
TX data
enable
SDO**
nIRQ
et bit
Enabling the Transmitter preloads the TX
Conf. Set.
el = 1
latch with 0xAAAA
T
tx_XTAL_ON
Power Man
et = 1
*
Synt.
PA
0xAA
Do not switch the et off here, because the
only stored into the internal register!
TX byte1 is not transmitted out
TX latch wr
TX byte1
Notes:
*T
** SDO is tri-state if nSEL is logic high.
0xAA
tx_XTAL_ON
is the start-up time of the PLL + PA with running crystal oscillator
TX latch wr
Dummy
TX byte
TX byte1
Power Man
et = 0
Fraction of the
Dummy byte
Conf. Set.
el = 0
Si4421
30

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