APA-EVAL-KIT Actel, APA-EVAL-KIT Datasheet - Page 82
APA-EVAL-KIT
Manufacturer Part Number
APA-EVAL-KIT
Description
MCU, MPU & DSP Development Tools ProAsic Plus Eval Kit
Manufacturer
Actel
Datasheet
1.APA075-FGG144.pdf
(178 pages)
Specifications of APA-EVAL-KIT
Processor To Be Evaluated
APA
Interface Type
ISP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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FIFO Reset
Notes:
1. During reset, either the enables (WRB and RBD) OR the clocks (WCLKS and RCKLS) must be low.
2. The plot shows the normal operation status.
Figure 2-45 • FIFO Reset
Table 2-68 • T
2 -7 2
Symbol t
CBRSH
CBRSS
ERSA
FRSA
RSL
THRSA
WBRSH
WBRSS
Note: During rest, the enables (WRB and RBD) must be high OR the clocks (WCLKS and RCKLS) must be low.
ProASIC
1
1
1
1
PLUS
xxx
T
J
J
Flash Family FPGAs
= 0°C to 110°C; V
= –55°C to 150°C, V
WCLKS or RCLKS ↑ hold from RESETB ↑
WCLKS or RCLKS ↓ setup to RESETB ↑
New EMPTY ↑ access from RESETB ↓
FULL ↓ access from RESETB ↓
RESETB low phase
EQTH or GETH access from RESETB ↓
WB ↓ hold from RESETB ↑
WB ↑ setup to RESETB ↑
WCLKS, RCLKS
EQTH, GETH
t ERSA , t FRSA
WRB/RBD
RESETB
DD
EMPTY
Description
t THRSA
FULL
DD
= 2.3 V to 2.7 V for Commercial/Industrial
1
1
= 2.3 V to 2.7 V for Military/MIL-STD-883
t CBRSS
v5.9
t RSL
Min.
1.5
1.5
3.0
3.0
7.5
4.5
1.5
1.5
Max.
t WBRSS
Units
ns
ns
ns
ns
ns
ns
ns
ns
t WBRSH
Cycle Start
Cycle Start
t CBRSH
Synchronous mode only
Synchronous mode only
Asynchronous mode only
Asynchronous mode only
Notes
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