APA-ISP-DEMO Actel, APA-ISP-DEMO Datasheet - Page 14
![no-image](/images/manufacturer_photos/0/0/8/actel_sml.jpg)
APA-ISP-DEMO
Manufacturer Part Number
APA-ISP-DEMO
Description
MCU, MPU & DSP Development Tools ProAsic Plus
Manufacturer
Actel
Datasheet
1.APA075-FGG144.pdf
(178 pages)
Specifications of APA-ISP-DEMO
Processor To Be Evaluated
APA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 14 of 178
- Download datasheet (6Mb)
Note: This figure shows routing for only one global path.
Figure 2-4 • High-Performance Global Network
Table 2-1 •
2 -4
Global Clock Networks (Trees)
Clock Spines/Tree
Total Spines
Top or Bottom Spine Height (Tiles)
Tiles in Each Top or Bottom Spine
Total Tiles
ProASIC
Bottom Spine
PLUS
Top Spine
Clock Spines
Global
Pads
Flash Family FPGAs
PAD RING
APA075
3,072
512
24
16
4
6
APA150
PAD RING
6,144
768
32
24
4
8
v5.9
APA300
1,024
8,192
32
32
4
8
APA450
12,288
1,024
12
48
32
4
High-Performance
Global Network
APA600
21,504
1,536
14
56
48
4
Global Networks
Global
Pads
Global Spine
Global Ribs
Scope of Spine
(Shaded area
plus local RAMs
and I/Os)
APA750
32,768
2,048
16
64
64
4
APA1000
56,320
2,560
22
88
80
4
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