MAXQ1004-KIT# Maxim Integrated Products, MAXQ1004-KIT# Datasheet - Page 12

• Manufacturer Part Number: MAXQ1004-KIT#
• Description: MCU, MPU & DSP Development Tools MAXQ1004 KIT MAXQ1004 KIT
• Manufacturer: Maxim Integrated Products

Specifications of MAXQ1004-KIT#

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1-Wire and SPI Authentication Microcontroller
The AES engine is a bidirectional block cipher support-
ing encryption and decryption for all three key lengths
recommended by the National Institute of Standards and
Technology (NIST). Secret keys can be generated by
an on-chip RNG and stored in a predetermined memory
location. The AES engine operates independently of the
processor, except for setting up an operation through
the AES Control register (AESC). The AESC register
provides AES engine operation status and option control.
The AES engine shares the cryptographic memory with
the 1-Wire communications peripheral. Application soft-
ware must ensure that the two peripherals do not access
the cryptographic memory at the same time or data in
the memory may be corrupted. Application software can
interrogate activity bits to ensure that one peripheral
does not interrupt the other. To perform an encryption
or decryption, the keys and data are loaded into the
cryptographic memory and the operation is started with
the appropriate write to the AESC register. Completion
of the operation can be detected by user firmware either
by polling the AESC register or through the use of an
interrupt.
The AES engine displays excellent performance. Based
on key size, the following encryption throughputs are
achieved:
• 128-bit key size—55 cycles (9.2µs at 6MHz)
• 192-bit key size—70 cycles (12.0µs at 6MHz)
• 256-bit key size—75 cycles (12.5µs at 6MHz)
Figure 1. ADC Block Diagram
12
Hardware AES Engine
INTERNAL REFERENCE
CONTROLLER
AVDD
ADC
1
0
ADCH
ADSCL
ADEN
ADCONV
ADCCLK
ADDATA
ADREF
DELTA-SIGMA
CONVERTER
10-BIT
An optional jitter injection feature reduces the effec-
tiveness of differential power analysis (DPA) attacks
against the device. Adding jitter causes random delays
in both the start and ending times of the calculation,
confounding attempts to determine the values in the AES
operation by measuring minute power fluctuations. When
active, the feature adds a variable random delay of 0
to 30 clock cycles to AES calculations. This is accom-
plished by randomly adding 0 to 15 clock cycles before
the AES operation is started, and adding 0 to 15 clock
cycles after the operation is complete.
The watchdog timer functions as the source of both the
timer timeout and the watchdog timer reset. The timeout
period can be programmed in a range of 2
tem clock cycles. An interrupt is generated when the time-
out period expires, if the interrupt is enabled. All watchdog
timer resets follow the programmed interrupt timeouts by
512 clock cycles. If the watchdog timer is not restarted
for another full interval in this time period, a system reset
occurs when the reset timeout expires. Table 1 shows
values that demonstrate the various interrupt timeouts
based on an internal clock frequency of 6MHz.
/2
0
1
AN0
SENSOR
Watchdog Timer
TEMP
12
to 2
29
sys-