DS31408DK Maxim Integrated Products, DS31408DK Datasheet - Page 6

• Manufacturer Part Number: DS31408DK
• Description: Power Management Modules & Development Tools DS31408DK DEMO KIT
• Manufacturer: Maxim Integrated Products

Output Clock Features
1588 Clock Features
General Features
Note to readers: This document is an abridged version of the full data sheet. To request the full data sheet, go to
www.maxim-ic.com/DS31408
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14 output clock signals in seven groups
Output clock groups OC1, OC2, OC3 have a very high-speed differential output (current-mode logic,
≤ 750MHz)
Output clock groups OC4–OC7 have a high-speed differential output (LVDS/LVPECL,
separate CMOS/TTL output (
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTU-1, OTU-2, OTU-3
Internal clock muxing allows each output group to slave to its associated DFS block, any of the APLLs, or
any input clock (after being divided and scaled)
Outputs sourced directly from APLLs have less than 1ps RMS output jitter
Outputs sourced directly from DFS blocks have approximately 40ps RMS output jitter
Optional 32-bit frequency divider per output
8kHz frame sync and 2kHz multiframe sync outputs have programmable polarity and pulse width and can
be disciplined by a 2kHz or 8kHz frame sync input
Per-output delay adjustment
Per-output enable/disable
All outputs disabled during reset
Initialized and steered by software on an external processor to follow an external 1588 master
2
4ns accuracy for input signal timestamping and output signal edge placement
Three time/frequency controls: direct time write, high-resolution frequency adjustment, and time adjustment
(i.e., frequency adjustment for an exact duration to achieve gradual, precise time change)
Programmable clock and time-alignment I/O to synchronize all 1588 elements in large systems
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Two flexible programmable event generators (PEG) can output one pulse per second (1PPS), one pulse per
period, and a wide variety of clock signals
Full support for dual redundant timing cards for high-reliability, fault-tolerant systems
Compatible with a wide variety of 1588 system architectures for 1588 ordinary clocks, boundary clocks,
and transparent clocks
SPI serial microprocessor interface
Four general-purpose I/O pins
Register set can be write-protected
Operates from a 12.8MHz, 25.6MHz, 10.24MHz, 20.48MHz, 10MHz, 20MHz, 19.44MHz, or 38.88MHz
local oscillator
On-chip watchdog circuit for the local oscillator
Internal compensation for local oscillator frequency error
-8
ns time resolution and 2
Can frequency-lock to an input clock signal from a master elsewhere in the system
Can timestamp (TS) an input alignment signal to time-lock to a master elsewhere in the system (e.g., 1PPS)
Can provide an output clock signal to slave components elsewhere in the system (e.g., 25MHz)
Can provide an output time alignment signal to slaves elsewhere in the system (e.g., 1PPS)
and a separate CMOS/TTL output (≤ 125MHz)
ABRIDGED DATA SHEET
and click on Request Full Data Sheet.
-32
ns frequency resolution
≤ 125MHz
)
≤ 312.5MHz)
DS31408
and a
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