DS31406DK Maxim Integrated Products, DS31406DK Datasheet - Page 4

• Manufacturer Part Number: DS31406DK
• Description: Power Management Modules & Development Tools DS31406 DEMO KIT DS31406 DEMO KIT
• Manufacturer: Maxim Integrated Products

Specifications of DS31406DK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Detailed Features
Input Clock Features
DPLL Features
Digital Frequency Synthesizer Features
Output APLL Features

































Two input clocks, differential or CMOS/TTL signal format
Input clocks can be any frequency from 2kHz up to 750MHz
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTU-1, OTU-2, OTU-3
Per-input fractional scaling (i.e. multiplying by ND where N is a 16-bit integer and D is a 32-bit integer and
N < D) to undo 64B/66B and FEC scaling (e.g., 64/66, 238/255, 237/255, 236/255)
Special mode allows locking to 1Hz input clocks
All inputs constantly monitored by programmable activity monitors and frequency monitors
Fast activity monitor can disqualify the selected reference after a few missing clock cycles
Frequency measurement and frequency monitor thresholds with 0.2ppm resolution
Three optional 2/4/8kHz frame-sync inputs
Very high-resolution DPLL architecture
Sophisticated state machine automatically transitions between free-run, locked, and holdover states
Revertive or nonrevertive reference selection algorithm
Programmable bandwidth from 0.5mHz to 400Hz
Separately configurable acquisition bandwidth and locked bandwidth
Programmable damping factor: 1.2, 2.5, 5, 10, or 20
Multiple phase detectors: phase/frequency and multicycle
Phase/frequency locking (360 capture) or nearest edge phase locking (180 capture)
Multicycle phase detection and locking (up to 8191UI) improves jitter tolerance and lock time
Phase build-out in response to reference switching for true hitless switching
Less than 1 ns output clock phase transient during phase build-out
Output phase adjustment up to 200ns in 6ps steps with respect to selected input reference
High-resolution frequency and phase measurement
Holdover frequency averaging over 1 second, 5.8 minute and 93.2 minute intervals
Fast detection of input clock failure and transition to holdover mode
Low-jitter frame sync (8kHz) and multiframe sync (2kHz) aligned with output clocks
Seven independently programmable DFS engines
Each DFS can synthesize any 2kHz multiple up to 77.76MHz
Per-DFS phase adjust (1/256UI steps)
Approximately 40ps RMS output jitter
Simultaneously produce three high-frequency, low-jitter, rates from the same reference clock, e.g.,
622.08MHz for SONET, 255/237*622.08MHz for OTU2, and156.25MHz for 10GE
Standard telecom output frequencies include 622.08MHz, 155.52MHz and 19.44MHz for SONET/SDH and
156.25MHz, 125MHz, and 25MHz for Synchronous Ethernet
Very high-resolution fractional scaling (i.e., noninteger multiplication)
Less than 1ps RMS output jitter
ABRIDGED DATA SHEET
DS31406
4