DS31404DK Maxim Integrated Products, DS31404DK Datasheet - Page 5

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DS31404DK

Manufacturer Part Number
DS31404DK
Description
Power Management Modules & Development Tools DS31404 Demonstratio 04 Demonstration Kit
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS31404DK

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Output Clock Features
General Features
Note to readers: This document is an abridged version of the full data sheet. To request the full data
sheet, go to
Eight output clock signals in four groups
Output clock groups OC1 and OC3 have a very high-speed differential output (current-mode logic,
≤ 750MHz)
Output clock groups OC4 and OC5 have a high-speed differential output (LVDS/LVPECL,
a separate CMOS/TTL ouptut (
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTU-1, OTU-2, OTU-3
Internal clock muxing allows each output group to slave to its associated DFS block, either of the APLLs, or
any input clock (after being divided and scaled)
Outputs sourced directly from APLLs have less than 1ps RMS output jitter
Outputs sourced directly from DFS blocks have approximately 40ps RMS output jitter
Optional 32-bit frequency divider per output
8kHz frame sync and 2kHz multiframe sync outputs have programmable polarity and pulse width and can
be disciplined by a 2kHz or 8kHz frame sync input
Per-output delay adjustment
Per-output enable/disable
All outputs disabled during reset
SPI serial microprocessor interface
Four general-purpose I/O pins
Register set can be write protected
Operates from a 12.8MHz, 25.6MHz, 10.24MHz, 20.48MHz, 10MHz, 20MHz, 19.44MHz, or 38.88MHz
local oscillator
On-chip watchdog circuit for the local oscillator
Internal compensation for local oscillator frequency error
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and a separate CMOS/TTL output (≤ 125MHz)
ABRIDGED DATA SHEET
≤ 125MHz
and click on Request Full Data Sheet.
)
≤ 312.5MHz)
DS31404
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