MAX17480EVKIT+ Maxim Integrated Products, MAX17480EVKIT+ Datasheet - Page 11

• Manufacturer Part Number: MAX17480EVKIT+
• Description: Power Management Modules & Development Tools EVAL KIT FOR MAX17480
• Manufacturer: Maxim Integrated Products

Specifications of MAX17480EVKIT+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

After the SMPS outputs reach the boot voltage, the
MAX17480 switches over to the serial-interface mode
when PGD_IN goes high. Any time during normal oper-
ation, a high-to-low transition on PGD_IN causes the
MAX17480 to slew all three internal DACs back to the
stored boot VIDs. The SVC and SVD inputs are dis-
abled during the time that PGD_IN is low. The serial
interface is re-enabled when PGD_IN goes high again
(see Table 8).
Table 7. Jumper JU4 Function (SHDN)
Table 8. Jumper JU1 Function (PGD_IN)
Table 9. Jumper JU2 Function (OPTION)
* Default position.
** VDD0 refers to CORE0 and VDD1 refers to CORE1 for the AMD CPU.
Note: In combined mode, the Address is NOT changed by the OPTION pin setting. The offset can still be set by any of the four levels
SHUNT POSITION
(shunt positions).
SHUNT POSITION
SHUNT POSITION
Not installed
Not installed
1-2*
1-5
1-3
1-4
1-2
2-3
1-2
2-3
System Power-Good Input (PGD_IN)
______________________________________________________________________________________
Connected to GND
Connected to OSC
Connected to VDD
Connected to 3.3V
OPTION PIN
Connected to VDD through
Connected to 2.5V through
Connected to U2, pin 58
Connected to U2, pin 59
Connected to GND
Connected to GND
100kΩ resistor R39
100k
PGD_IN PIN
resistor R9
PIN
OFFSET ENABLED
MAX17480 Evaluation Kit
—
The SVC and SVD inputs are disabled during the time PGD_IN
is low.
The serial interface is re-enabled when PGD_IN goes high again.
The MAX17480 switches over to the serial-interface mode when
PGD_IN goes high.
—
Shutdown mode, SMPS output voltages disabled.
VCORE0 = 0V and VOUT_NB = 0V.
SMPS output voltages enabled.
VCORE0 and VOUT_NB voltages are set by SVC and SVD inputs.
0
0
1
1
The +12.5mV offset and the address change features
of the MAX17480 can be selectively enabled and dis-
abled by the OPTION pin setting. When the offset is
enabled, setting the PSI_L bit to 0 disables the offset,
reducing power consumption in the low-power state.
Refer to the Core SMPS Offset section in the MAX17480
IC data sheet for a detailed description of this feature.
When configured in separate mode, the address of the
core SMPSs (VCORE0 and VCORE1) can be exchanged,
allowing for flexible layout of the MAX17480 with
respect to the CPU placement on the same or opposite
sides of the PCB. Table 9 shows the OPTION pin volt-
age levels and the features that are enabled.
SMPS1 ADDRESS**
BIT 1 (VDD0)
BIT 2 (VDD1)
BIT 1 (VDD0)
BIT 2 (VDD1)
MAX17480 OUTPUT
MAX17480 OUTPUT
Offset and Address Change for Core
SMPS2 ADDRESS**
SMPSs (OPTION)
BIT 2 (VDD1)
BIT 1 (VDD0)
BIT 2 (VDD1)
BIT 1 (VDD0)
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