DS8005-KIT# Maxim Integrated Products, DS8005-KIT# Datasheet - Page 11

• Manufacturer Part Number: DS8005-KIT#
• Description: Power Management Modules & Development Tools DS8005 EVAL KIT DS8005 EVAL KIT
• Manufacturer: Maxim Integrated Products

Specifications of DS8005-KIT#

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

load current. Current to and from the card I/O lines is
limited internally to 15mA. The maximum frequency on
these lines is 1MHz.
The device powers up with the card interface in the
inactive mode. Minimal circuitry is active while waiting
for the host to initiate a smart card session.
• All card contacts are inactive (approximately 200Ω to
• The I/OIN pin in the high-impedance state (11kΩ
• Voltage generators are stopped.
• XTAL oscillator is running (if included in the device).
• Voltage supervisor is active.
• The internal oscillator is running at its low frequency.
After power-on and the reset delay, the host microcon-
troller can monitor card presence with signals OFF and
CMDVCC, as shown in Table 2.
Figure 3. Activation Sequence Using RSTIN and CMDVCC
GND).
pullup resistor to V
CMDVCC
RSTIN
CLK_
RST_
V
I/OIN
I/O_
CC_
______________________________________________________________________________________
DD
Activation Sequence
).
t
0
t
1
Inactive Mode
t
2
t
3
t
4
t
5
If the card is in the reader (if PRES_ is active), the host
microcontroller can begin an activation sequence (start
a card session) by pulling CMDVCC low. The following
events form an activation sequence (Figure 3):
1) CMDVCC is pulled low.
2) The internal oscillator changes to high frequency (t
3) The voltage generator is started (between t
Table 2. Card Presence Indication
= t
ACT
SEL_AB
SEL_AB
High
High
High
High
Low
Low
Low
Low
Smart Card Interface
OFF2
High
High
High
High
OFF
Low
Low
Low
Low
CMDVCC
CMDVCC
High
High
High
High
High
High
High
High
Card A present.
Card A not present.
Card B present.
Card B not present.
Card B present.
Card B not present.
Card A present.
Card A not present.
ATR
STATUS
STATUS
0
and t
1
0
).
).
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