DS26514DK Maxim Integrated Products, DS26514DK Datasheet - Page 257

• Manufacturer Part Number: DS26514DK
• Description: Power Management Modules & Development Tools 4-Port T1-E1-J1 Tran Transceiver Demo Kit
• Manufacturer: Maxim Integrated Products

Specifications of DS26514DK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.8
10.8.1 Transmit HDLC-256 Register Definitions
Table 10-30. Transmit Side HDLC-256 Register Map
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 6: Transmit Packet Start Disable (TPSD) – When 0, the Transmit Packet Processor will continue sending
packets after the current packet end. When 1, the Transmit Packet Processor will stop sending packets after the
current packet end.
Bit 5: Transmit FCS Error Insertion (TFEI) – When 0, the calculated FCS (inverted CRC-16) is appended to the
packet. When 1, the inverse of the calculated FCS (non-inverted CRC-16) is appended to the packet causing a
FCS error. This bit is ignored if transmit FCS processing is disabled (TFPD = 1).
Bit 4: Transmit Inter-frame Fill Value (TIFV) – When 0, inter-frame fill is done with the flag sequence (7Eh).
When 1, inter-frame fill is done with all ‘1’s.
Bit 3: Transmit Bit Reordering Enable (TBRE) – When 0, bit reordering is disabled (The first bit transmitted is the
LSB of the Transmit FIFO Data byte TFD[0]). When 1, bit reordering is enabled (The first bit transmitted is the MSB
of the Transmit FIFO Data byte TFD[7]).
Bit 2: Transmit Data Inversion Enable (TDIE) – When 0, the outgoing data is directly output from packet
processing. When 1, the outgoing data is inverted before being output from packet processing.
Bit 1: Transmit FCS Processing Disable (TFPD) – This bit controls whether or not a FCS is calculated and
appended to the end of each packet. When 0, the calculated FCS bytes are appended to the end of the packet.
When 1, the packet is transmitted without a FCS.
Bit 0: Transmit FIFO Reset (TFRST) – When 0, the Transmit FIFO will resume normal operations, however, data
is discarded until a start of packet is received after RAM power-up is completed. When 1, the Transmit FIFO is
Rev: 101608
ADDRESS
150Ah
150Bh
150Ch
150Dh
150Eh
1500h
1501h
1502h
1503h
1504h
1505h
1506h
1507h
1508h
1509h
150Fh
HDLC-256 Register Definitions
--
7
0
TH256FDR1
TH256FDR2
TH256SRIE
REGISTER
TH256CR1
TH256CR2
TH256SR1
TH256SR2
TH256SRL
--
--
--
--
--
--
--
--
TPSD
6
0
Transmit HDLC-256 Control Register 1
Transmit HDLC-256 Control Register 2
Transmit HDLC-256 FIFO Data Register 1
Transmit HDLC-256 FIFO Data Register 2
Transmit HDLC-256 Status Register 1
Transmit HDLC-256 Status Register 2
Transmit HDLC-256 Status Register Latched
Unused
Transmit HDLC-256 Status Register Interrupt Enable
Unused
Unused
Unused
Unused
Unused
Unused
Unused
TH256CR1
Transmit HDLC-256 Transmit Control Register 1
1500h + (20h x (n-1)) : where n = 1 to 4
TFEI
5
0
REGISTER DESCRIPTION
TIFV
4
0
TBRE
3
0
DS26514 4-Port T1/E1/J1 Transceiver
TDIE
2
0
TFPD
1
0
TFRST
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0
0