WS02-CXPC1-EV2.0 Omron, WS02-CXPC1-EV2.0 Datasheet - Page 24

• Manufacturer Part Number: WS02-CXPC1-EV2.0
• Description: Development Software
• Manufacturer: Omron

Specifications of WS02-CXPC1-EV2.0

• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: WS02CXPC1EV20

SRM1
J INSTRUCTION SET SUMMARY
The following table lists the SRM1(-V2) instructions that have
fixed function codes. Each instruction is listed by mnemonic and
by instruction name. Use the numbers in the leftmost column as
the left digit and the number in the column heading as the right
digit of the function code.
J EXPANSION INSTRUCTIONS WITHOUT DEFAULT FUNCTION CODES
Note: *SCL(66), NEG(––), PID(––), and ZCP (––) are supported by the SRM1-C0j-V2 CPUs only.
24
Left
digit
0
1
2
3
4
5
6
7
8
9
Mnemonic
FCS(@)
HEX(@)
NEG(@)*
PID*
STUP(@)
ZCP*
0
NOP
No
operation
SFT
Shift
register
CMP
Compare
ADD(@)
BCD add
STC(@)
Set carry
ADB(@)
Binary
add
CMPL
Double
compare
XFER(@)
Block
transfer
DIST(@)
Single
word
distribute
---
Name
FCS CALCULATE
ASCII-TO-HEXADECIMAL
2’S COMPLEMENT
PID CONTROL
CHANGE RS-232C SETUP
AREA RANGE COMPARE
1
END
End
KEEP
Keep
MOV(@)
Move
SUB(@)
BCD
subtract
CLC(@)
Clear
carry
SBB(@)
Binary
subtract
INI(@)
Mode
control
BSET(@)
Block set
COLL(@)
Data
collect
SBS(@)
Subrou-
tine
entry
2
IL
Interlock
CNTR
Revers-
ible
counter
MVN(@)
Move not
MUL(@)
BCD
multiply
---
MLB(@)
Binary
multiply
PRV(@)
PV read
---
MOVB(@)
Move bit
SBN
Subrou-
tine
define
3
ILC
Interlock
clear
DIFU
Differenti-
ate up
BIN(@)
BCD to
binary
DIV(@)
BCD
divide
---
DVB(@)
Binary
divide
CTBL(@)
Compare
table load
XCHG(@)
Data
exchange
MOVD(@)
Move digit
RET
Subrou-
tine
return
4
JMP
Jump
DIFD
Differenti-
ate down
BCD(@)
Binary to
BCD
ANDW
(@)
Logical
AND
---
ADDL(@)
Double
BCD add
---
SLD(@)
One digit
shift left
SFTR(@)
Revers-
ible shift
register
---
Right digit
The shaded areas are function codes to which expansion
instructions are allocated by default or to which the user can
allocate expansion instructions. The expansion instructions
shown at the bottom of the page can be substituted for the ones
with default function codes.
5
JME
Jump end
TIMH
High-
speed
timer
ASL(@)
Shift left
ORW(@)
Logical
OR
---
SUBL(@)
Double
BCD
subtract
---
SRD(@)
One digit
shift right
TCMP(@)
Table
compare
---
6
FAL(@)
Failure
alarm and
reset
WSFT(@)
Word shift
ASR(@)
Shift right
XORW
(@)
Exclusive
OR
MSG(@)
Message
display
MULL(@)
Double
BCD
multiply
SCL(@)
Scaling
(See
Note)
MLPX(@)
4-to-16
decoder
ASC(@)
ASCII
convert
---
7
FALS
Severe
failure
alarm
ASFT(@)
Asynchro-
nous shift
register
ROL(@)
Rotate left
XNRW
(@)
Exclusive
NOR
RXD(@)
Receive
DIVL(@)
Double
BCD
divide
BCNT(@)
Bit
counter
DMPX(@)
16-to-4
encoder
---
---
8
STEP
Step
define
---
ROR(@)
Rotate
right
INC(@)
Increment
TXD(@)
Transmit
---
BCMP(@)
Block
compare
SDEC(@)
7-seg-
ment
decoder
---
---
9
SNXT
Step start
---
COM(@)
Comple-
ment
DEC(@)
Decre-
ment
---
---
STIM(@)
Interval
timer
---
INT(@)
Interrupt
control
MCRO
(@)
Macro
SRM1