CRD-49530-USB Cirrus Logic Inc, CRD-49530-USB Datasheet - Page 12

• Manufacturer Part Number: CRD-49530-USB
• Description: Audio Modules & Development Tools Eval Bd 32-Bit Aud Dcdr & Prgrmble DSP
• Manufacturer: Cirrus Logic Inc

Specifications of CRD-49530-USB

• Product: Audio Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CRD49530-USB System Description
CRD49530-USB User’s Manual
1-7
1.3.10.2 Clock and Data Flow for S/PDIF Input
The CS4953xx always masters its output clocks (DSP_SCLK/DSP_LRCLK).
The S/PDIF clocking architecture is used when any S/PDIF RX is used as an audio source, whether S/
PDIF is the only audio input or is used at the same time as ADC audio (i.e. any S/PDIF RX is selected as
described in
used to select on-board audio sources.
MCLK recovered from the incoming S/PDIF stream must be MCLK for the system, and the codec masters
the input clocks (MUXED_SCLK/MUXED_LRCLK) of the CS4953xx. In this configuration the internal
multiplexer of the CS8416 routes the recovered MCLK to MUXED_MCLK.
Note: MUXED_MCLK is the clock signal that is driven by the CS8416’s RMCK pin. The CS8416
MUXED_LRCLK
provides the recovered clock from the S/PDIF input unless it loses signal lock, in which case the
CS8416 passes the DSP clock (XTAL_OUT) that it receives on the OMCK pin.
MUXED_MCLK
MUXED_SCLK
DSP_LRCLK
Clock Name
DSP_SCLK
DAI
CS4953xx
"USB (I2S) Audio Input" on page
CS8416
PLL
Clock Master Source
DAO
MUXED_MCLK
MUXED_MCLK
MUXED_MCLK
MUXED_MCLK
CS4953xx
MUXED_DAI[3:0]
MUXED_LRCLK
MUXED_SCLK
S/PDIF Input
MUXED_MCLK
DSP_SCLK
DSP_LRCLK
DSP_DA0[3:0]
Figure 1-4. S/PDIF Clocking
Table 1-1. ADC Clocking
Copyright 2008 Cirrus Logic
Figure 1-4
4-5), and the audio input source multiplexer (U1, U2) is
Clock Driver
illustrates this clocking configuration.
CS4953xx
CS4953xx
CS42448
CS42448
CS8416
64*Output Fs (default)
64*Input Fs (default)
1*Input Fs (default)
Clock Frequency
24.576 MHz
SDIN
Input Fs
SDOUT
CS42448
DS705RD3