EB52F3C50N-10.240M Ecliptek, EB52F3C50N-10.240M Datasheet

EB52F3C50N-10.240M

Manufacturer Part Number

EB52F3C50N-10.240M

Description

Manufacturer

Ecliptek

Datasheet

1.EB52F3C50N-10.240M.pdf (4 pages)

Specifications of EB52F3C50N-10.240M

Output Level

LVCMOS

Symmetry Max

60%

Operating Supply Voltage (typ)

3.3

Mounting Style

Through Hole

Screening Level

Commercial

Rad Hardened

Lead Free Status / RoHS Status

Not Compliant

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ELECTRICAL SPECIFICATIONS

Nominal Frequency

Frequency Stability

Frequency Stability vs. Input Voltage

Aging at 25°C

Frequency Stability vs. Load

Operating Temperature Range

Supply Voltage

Input Current

Output Voltage Logic High (Voh)

Output Voltage Logic Low (Vol)

Rise/Fall Time

Duty Cycle

Load Drive Capability

Output Logic Type

Control Voltage

Internal Trim

Modulation Bandwidth

Input Impedance

Phase Noise

Storage Temperature Range

ENVIRONMENTAL & MECHANICAL SPECIFICATIONS

Fine Leak Test

Gross Leak Test

Lead Integrity

Mechanical Shock

Resistance to Soldering Heat

Resistance to Solvents

Solderability

Temperature Cycling

Vibration

EB52F3C50N-10.240M

www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 2/10/2011 | Page 1 of 4

Series

3.3Vdc 14-Pin DIP LVCMOS TCXO

Operating Temperature Range

-20°C to +70°C

10.240MHz

±5.0ppm Maximum (Inclusive of Operating Temperature Range)

±0.3ppm Maximum (±5%)

±1ppm/Year Maximum

±0.2ppm Maximum (±2pF)

-20°C to +70°C

3.3Vdc ±5%

10mA Maximum

90% of Vdd Minimum

10% of Vdd Maximum

10nSec Maximum (Measured at 20% to 80% of waveform)

50% ±10% (Measured at 50% of waveform)

15pF Maximum

CMOS

None (No Connect on Pin 1)

±3ppm Minimum (Top of Can)

10kHz Minimum (Measured at -3dB with a Control Voltage of 1.65Vdc)

10kOhms Typical

-70dBc at 10Hz Offset, -100dBc at 100Hz Offset, -130dBc at 1kHz Offset, -140dBc at 10kHz Offset, -

145dBc at 100kHz Offset

-40°C to +85°C

MIL-STD-883, Method 1014 Condition A (Internal Crystal Only)

MIL-STD-883, Method 1014 Condition C (Internal Crystal Only)

MIL-STD-883, Method 2004

MIL-STD-202, Method 213 Condition C

MIL-STD-202, Method 210

MIL-STD-202, Method 215

MIL-STD-883, Method 2003

MIL-STD-883, Method 1010

MIL-STD-883, Method 2007 Condition A

EB52F3 C 50 N -10.240M

Frequency Stability

±5.0ppm Maximum

Control Voltage

None (No Connect on Pin 1)

Nominal Frequency

10.240MHz

Related parts for EB52F3C50N-10.240M

EB52F3C50N-10.240M Summary of contents

Page 1

... EB52F3C50N-10.240M Series 3.3Vdc 14-Pin DIP LVCMOS TCXO Operating Temperature Range -20°C to +70°C ELECTRICAL SPECIFICATIONS Nominal Frequency 10.240MHz Frequency Stability ±5.0ppm Maximum (Inclusive of Operating Temperature Range) Frequency Stability vs. Input Voltage ±0.3ppm Maximum (±5%) Aging at 25°C ±1ppm/Year Maximum Frequency Stability vs. Load ± ...

Page 2

... EB52F3C50N-10.240M MECHANICAL DIMENSIONS (all dimensions in millimeters) Internal Trim Access 4.8 ±0.3 Hole Ø3.5 ±0.5 11.7 MARKING ±0.5 ORIENTATION 2.5 ±0.3 18.3 ±0.5 OUTPUT WAVEFORM V OH 80% of Waveform 50% of Waveform 20% of Waveform V OL Fall Time www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 2/10/2011 | Page 4.0 ± ...

Page 3

... EB52F3C50N-10.240M Test Circuit for CMOS Output + Current Meter + + Power Voltage Supply Meter _ _ Note 1: An external 0.1µF low frequency tantalum bypass capacitor in parallel with a 0.01µF high frequency ceramic bypass capacitor close to the package ground and V Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth (> ...

Page 4

... EB52F3C50N-10.240M Recommended Solder Reflow Methods Max S T Min S Low Temperature Solder Bath (Wave Solder) T MAX to T (Ramp-up Rate Preheat - Temperature Minimum (T MIN Temperature Typical (T TYP Temperature Maximum (T MAX Time (t MIN) S Ramp-up Rate ( Time Maintained Above: - Temperature ( Time ( Peak Temperature ( Target Peak Temperature (T ...

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