HA7210IBZ Intersil, HA7210IBZ Datasheet - Page 4

• Manufacturer Part Number: HA7210IBZ
• Manufacturer: Intersil

Specifications of HA7210IBZ

• Output Level: CMOS
• Symmetry Max: 60%
• Operating Supply Voltage (typ): 5
• Pin Count: 8
• Mounting Style: Surface Mount
• Screening Level: Industrial
• Product Height (mm): 1.5mm
• Product Depth (mm): 4mm
• Product Length (mm): 5mm
• Rad Hardened: No
• Package / Case: SOIC N
• Lead Free Status / RoHS Status: Compliant

Test Circuit
In production the HA7210 is tested with a 32kHz and a
1MHz crystal. However for characterization purposes data
was taken using a sinewave generator as the frequency
determining element, as shown in Figure 1. The 1V
is a smaller amplitude than what a typical crystal would
generate so the transitions are slower. In general the
Generator data will show a “worst case” number for I
duty cycle, and rise/fall time. The Generator test method is
useful for testing a variety of frequencies quickly and
provides curves which can be used for understanding
performance trends. Data for the HA7210 using crystals has
also been taken. This data has been overlaid onto the
generator data to provide a reference for comparison.
Application Information
Theory Of Operation
The HA7210 is a Pierce Oscillator optimized for low power
consumption, requiring no external components except for a
bypass capacitor and a Parallel Mode Crystal. The Simplified
Block Diagram shows the Crystal attached to pins 2 and 3, the
Oscillator input and output. The crystal drive circuitry is detailed
showing the simple CMOS inverter stage and the P-channel
device being used as biasing resistor R
operate mostly in its linear region increasing the amplitude of
the oscillation until limited by its transconductance and voltage
rails, V
center the oscillating waveform at the input threshold. Do not
interfere with this bias function with external loads or excessive
leakage on pin 2. Nominal value for R
frequency range to 7MΩ in the highest frequency range.
The HA7210 optimizes its power for 4 frequency ranges
selected by digital inputs Freq1 and Freq2 as shown in the
Block Diagram. Internal pull up resistors (constant current
0.4µA) on Enable, Freq1 and Freq2 allow the user simply to
leave one or all digital inputs not connected for a
corresponding “1” state. All digital inputs may be left open for
10kHz to 100kHz operation.
A current source develops 4 selectable reference voltages
through series resistors. The selected voltage, V
buffered and used as the negative supply rail for the
oscillator section of the circuit. The use of a current source in
the reference string allows for wide supply variation with
minimal effect on performance. The reduced operating
DD
1V
and V
P-P
50Ω
RN
0.1µF
. The inverter is self biasing using R
1000pF
+5V
FIGURE 1.
1
2
3
4
4
HA7210
F
F
is 17MΩ in the lowest
. The inverter will
8
7
6
5
C
L
ENABLE
FREQ 2
FREQ 1
18pF
RN
P-P
, is
V
DD
F
OUT
to
input
,
HA7210
voltage of the oscillator section reduces power consumption
and limits transconductance and bandwidth to the frequency
range selected. For frequencies at the edge of a range, the
higher range may provide better performance.
The OSC OUT waveform on pin 3 is squared up through a series
of inverters to the output drive stage. The Enable function is
implemented with a NAND gate in the inverter string, gating the
signal to the level shifter and output stage. Also during Disable
the output is set to a high impedance state useful for minimizing
power during standby and when multiple oscillators are OR’ed to
a single node.
Design Considerations
The low power CMOS transistors are designed to consume
power mostly during transitions. Keeping these transitions
short requires a good decoupling capacitor as close as
possible to the supply pins 1 and 4. A ceramic 0.1µF is
recommended. Additional supply decoupling on the circuit
board with 1µF to 10µF will further reduce overshoot, ringing
and power consumption. The HA7210, when compared to a
crystal and inverter alone, will speed clock transition times,
reducing power consumption of all CMOS circuitry run from
that clock.
Power consumption may be further reduced by minimizing the
capacitance on moving nodes. The majority of the power will
be used in the output stage driving the load. Minimizing the
load and parasitic capacitance on the output, pin 5, will play
the major role in minimizing supply current. A secondary
source of wasted supply current is parasitic or crystal load
capacitance on pins 2 and 3. The HA7210 is designed to work
with most available crystals in its frequency range with no
external components required. Two 15pF capacitors are
internally switched onto crystal pins 2 and 3 on the HA7210 to
compensate the oscillator in the 10kHz to 100kHz frequency
range.
The supply current of the HA7210 may be approximately
calculated from the equation:
I
EXAMPLE #1:
V
I
I
Measured I
EXAMPLE #2:
V
I
I
Measured I
DD
DD
DD
DD
DD
DD
DD
I
V
f
C
DD
OSC
(Disabled) = 4.5µA (Figure 10)
DD
L
= I
= 4.5µA + (5V)(100kHz)(30pF) = 19.5µA
(Disabled) = 75µA (Figure 9)
= 75µA + (5V)(5MHz)(30pF) = 825µA
= 5V, f
= 5V, f
= Output (pin 5) load capacitance
= Total supply current
DD
= Total voltage from V
= Frequency of Oscillation
(Disabled) + V
DD
DD
OSC
OSC
= 20.3µA
= 809µA
= 100kHz, C
= 5MHz, C
DD
L
× f
L
= 30pF
DD
OSC
= 30pF
(pin 1) to V
× C
L
where:
SS
(pin 4)