APD-256G064-1 Vishay, APD-256G064-1 Datasheet - Page 2
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APD-256G064-1
Manufacturer Part Number
APD-256G064-1
Description
Plasma Displays PLASMA DSPLY W/CNVTR
Manufacturer
Vishay
Datasheet
1.APD256G0640001G01.pdf
(3 pages)
Specifications of APD-256G064-1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Document Number: 37020
Revision 05-Dec-00
DESCRIPTION OF INPUT SIGNALS
DOT CLOCK - This signal enters the SERIAL DATA on each
low to high transition. A total of 256 DOT CLOCK transitions
must be present for each line of column/anode data.
SERIAL DATA - This signal presents the pixel data in
positive logic format. A logic one represents a lit pixel and a
logic zero represents an extinguished pixel. Data is entered
from right to left. The first pixel data entered will represent
the leftmost pixel in the row.
COLUMN LATCH - This signal latches the pixel data into the
driver outputs. When the COLUMN LATCH signal goes to
logic one the data entered previously will fall through to the
driver outputs. When the signal returns to a logic zero, the
data is latched and the shift register is now ready to accept
the next row of data. Must be held low while entering new
SERIAL DATA.
DISPLAY ENABLE - This signal enables the output drivers.
Using a duty cycle control, this signal may also be used for
intensity control. The DISPLAY ENABLE must be at logic
zero before the COLUMN LATCH signal transitions. To
avoid display blurring, the ROW CLOCK signal should also
transition while DISPLAY ENABLE is a logic zero. It is
recommended that this signal remain low for 10µS min.
ROW DATA - This signal is the first line marker for the scan.
This input should be held high to correspond to the first row
of pixel data.
ROW CLOCK - This signal clocks ROW DATA on the falling
edge. The ROW CLOCK signal is repetitive and must be
present for proper scanning of the display module.
The APD-256G064-1 has a unique input protection circuit
that assures the column drivers stay blanked on power up.
The protection circuit unblanks the column drivers when the
ROW CLOCK signal begins (i.e. the display begins scan-
ning).
AMP #640445-5 or equivalent.
(Mates with AMP 640428-5, MOLEX 09-05-3051 or equivalent.)
AMP #103309-2 or equivalent.
(Mates with AMP 746195-2, MOLEX 39-27-1146 or equivalent.)
P3, POWER CONNECTOR
P2, DATA CONNECTOR
ORDERING INFORMATION
PIN DESCRIPTION
PIN
1
2
3
4
5
PIN
11
13
Display Module with Drivers, TTL Interface and On Board Converter............................................................... ................ APD-256G064-1
Data Connector Kit...................................................................................................................................................... ................ 280105-05
Power Connector Kit................................................................................................................................................... ................ 280108-13
Video Controller (+5V) Parallel and Serial Interface...................................................................................................... ................. PDS-500
Video Controller (+12V) Parallel and Serial Interface................................................................................................. ................ PDS-500-1
1
3
5
7
9
DESCRIPTION
DISPLAY ENABLE
ROW DATA
ROW CLOCK
COLUMN LATCH
DOT CLOCK
SERIAL DATA
No connect
SIGNAL
GND
VDC
V
KEY
GND
cc
PIN
10
12
14
2
4
6
8
DESCRIPTION
V
DC Converter Supply
Logic Supply
Used to key connector
V
bb
bb
and V
DESCRIPTION
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
cc
Display Enable
Row Data
Display Enable
Row Clock
Row Clock
Column Latch
Dot Clock
Serial Data
LOGIC AND DATA TIMING
PARAMETER
t
t
t
t
t
t
t
1
2
3
4
5
6
7
t
1
1st Bit of Row Will Appear in Leftmost Column
MINIMUM
0
t
t
6
5
0
0
100
25
75
75
—
5
1
1
1
1
Positive Edge x 256
t
2
2
2
2
TYPICAL
70
—
—
—
—
—
—
APD-256G064-1
t
3
t
4
254 255
62
MAXIMUM
62
t
7
Vishay Dale
200
63
—
—
—
—
—
—
63
www.vishay.com
0
0
UNITS
1
1
nS
uS
uS
Hz
nS
nS
nS
3