AEAT-84AD-LBSF0 Avago Technologies US Inc., AEAT-84AD-LBSF0 Datasheet - Page 4

Quadrant/Circular Detector,Module C

AEAT-84AD-LBSF0

Manufacturer Part Number
AEAT-84AD-LBSF0
Description
Quadrant/Circular Detector,Module C
Manufacturer
Avago Technologies US Inc.
Series
AEAT-84ADr
Datasheet

Specifications of AEAT-84AD-LBSF0

Encoder Type
Optical
Output Type
Gray Code (Absolute)
Pulses Per Revolution
16384
Voltage - Supply
5VDC
Actuator Type
10mm Geared Center
Detent
No
Built In Switch
No
Mounting Type
Chassis Mount
Termination Style
Pin Strip
Output
Digital
Operating Temperature Range
- 40 C to + 125 C
Product
Optical
Technology
Rotary
Detents
No
Motion
Rotary
Index Output
Not Indexed
Encoder Signal
Digital Square Wave
Shaft Style
Hollow
Operating Temperature Min Deg. C
-40C
Operating Temperature Max Deg. C
125C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Orientation
-
Rotational Life (cycles Min)
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AEAT-84AD-LBSF0
Manufacturer:
AVAGO
Quantity:
101
Gray code-generation
For the readout schematic of the
multi-turn code gears, i.e. with the
user’s microcontroller, there must
be a logical replication of the V-bit
multiplexers. This can be done by a
bit manipulation or by look up
tables. Care needs to be taken with
the real time readout conditions.
The procedure is as follows :
1. The 3 bits ( MTDAT[2:0] ) of each
2. Synchronous to the readout of
3. The bit change of the complete
The logic diagram for ONE gear is
shown in the following diagram (V-
bit-Multiplexer), Figure 4.
4
gear (C1[2:0] to C7[2:0]) are
continuously de-multiplexed.
Thus there are maximal 3 bits x
7gears = 21-bit AEAT-84AD data
in parallel.
the single turn absolute encoder,
those
(depending on the MSB bit, i.e.
SEL-bit, of the single turn
encoder)
complemented to the complete
Gray code word (cascading).
Gray code will be synchronized
by the single turn absolute
encoder and thus electronically
eliminating gear play.
AEAT-84AD
needs
to
bits
be
Logic Diagram
Figure 4. Logic Diagram and Truth Table for one of the gear wheels
From MTDAT-Demux
(Code-Wheel x)
Cx[2]
Cx[1]
Cx[0]
SEL
SEL
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Cx[0]
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
XOR
Cx[1]
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
Cx[2]
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
0
1
S
S
D1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
Y
Y
D2
4x MUX2
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1 S
0
1 S
V2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Y
Y
V2
(V-Bit2)
D2
(Data-Bit2)
D1
(Data-Bit1)

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