PN5120A0HN1/C2,151 NXP Semiconductors, PN5120A0HN1/C2,151 Datasheet - Page 45

• Manufacturer Part Number: PN5120A0HN1/C2,151
• Description: IC TRANSMISSION MOD 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN1/C2,151

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
PN512
Product data sheet
COMPANY PUBLIC
9.2.2.14 ManualRCVReg
Allows manual fine tuning of the internal receiver.
Remark: For standard applications it is not recommended to change this register settings.
Table 72.
Table 73.
Bit
7
6
5
4
3
2
1 to 0
Access
Rights
Symbol
-
FastFilt
MF_SO
Delay MF_SO If this bit is set to logic 1, the Signal at SIGOUT-pin is delayed, so that
Parity Disable
LargeBWPLL
ManualHPCF
HPFC
ManualRCVReg register (address 1Dh); reset value: 00h, 00000000b
Description of ManualRCVReg bits
RFU
7
0
All information provided in this document is subject to legal disclaimers.
MF_SO
FastFilt
Rev. 3.6 — 10 March 2011
r/w
6
Description
Reserved for future use.
If this bit is set to logic 1, the internal filter for the Miller-Delay Circuit is
set to Fast mode.
Note: This bit should only set to logic 1, if Millerpulses of less than
400 ns Pulse length are expected. At 106 kBaud the typical value is
3 us.
in SAM mode the Signal at SIGIN must be 128/fc faster compared to
the ISO/IEC 14443A, to reach the ISO/IEC 14443A restrictions on the
RF-Field.
Note: This delay shall only be activated for setting bits SigOutSel to
(1110b) or (1111b) in register TxSelReg.
If this bit is set to logic 1, the generation of the Parity bit for
transmission and the Parity-Check for receiving is switched off. The
received Parity bit is handled like a data bit.
Set to logic 1, the bandwidth of the internal PLL used for clock
recovery is extended.
Set to logic 0, the HPCF bits are ignored and the HPCF settings are
adapted automatically to the receiving mode. Set to logic 1, values of
HPCF are valid.
Selects the High Pass Corner Frequency (HPCF) of the filter in the
internal receiver chain
00 For signals with frequency spectrum down to 106 kHz.
01 For signals with frequency spectrum down to 212 kHz.
10 For signals with frequency spectrum down to 424 kHz.
11 For signals with frequency spectrum down to 848 kHz
111336
MF_SO
Delay
r/w
5
Disable
Parity
r/w
4
LargeBW
PLL
r/w
3
Manual
HPCF
r/w
2
Transmission module
© NXP B.V. 2011. All rights reserved.
r/w
1
PN512
HPFC
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r/w
0