PN5120A0HN1/C2,157 NXP Semiconductors, PN5120A0HN1/C2,157 Datasheet - Page 5
PN5120A0HN1/C2,157
Manufacturer Part Number
PN5120A0HN1/C2,157
Description
IC TRANSMISSION MOD 32-HVQFN
Manufacturer
NXP Semiconductors
Datasheet
1.PN5120A0HN1C2118.pdf
(125 pages)
Specifications of PN5120A0HN1/C2,157
Rf Type
Read / Write
Frequency
13.56MHz
Features
ISO14443-A, ISO14443-B
Package / Case
32-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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6. Block diagram
PN512
Product data sheet
COMPANY PUBLIC
The analog interface handles the modulation and demodulation of the analog signals
according to the Card Receiving mode, Reader/Writer mode and NFCIP-1 mode
communication scheme.
The RF level detector detects the presence of an external RF-field delivered by the
antenna to the RX pin.
The Data mode detector detects a MIFARE, FeliCa or NFCIP-1 mode in order to prepare
the internal receiver to demodulate signals, which are sent to the PN512.
The communication (S
transfer speeds above 424 kbit/s and digital signals to communicate to a secure IC.
The contactless UART manages the protocol requirements for the communication
protocols in cooperation with the host. The FIFO buffer ensures fast and convenient data
transfer to and from the host and the contactless UART and vice versa.
Various host interfaces are implemented to meet different customer requirements.
Fig 1. Simplified block diagram of the PN512
ANTENNA
All information provided in this document is subject to legal disclaimers.
INTERFACE
ANALOG
Rev. 3.6 — 10 March 2011
2
C) interface provides digital signals to support communication for
111336
CONTACTLESS
UART
BUFFER
FIFO
REGISTER BANK
SERIAL UART
I
2
C-BUS
SPI
Transmission module
© NXP B.V. 2011. All rights reserved.
001aaj627
PN512
HOST
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