JN5139/001,515 NXP Semiconductors, JN5139/001,515 Datasheet - Page 43

• Manufacturer Part Number: JN5139/001,515
• Description: IC MCU 32BIT 56QFN
• Manufacturer: NXP Semiconductors

Specifications of JN5139/001,515

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

value of the generated RTS (negated if the receive FIFO fill level is 15 and another character starts to be received,
and asserted when the receive FIFO is read), and only transmits data when the incoming CTS is asserted.
Software can read characters, one byte at a time, from the Receive FIFO and can also write to the Transmit FIFO,
one byte at a time. The Transmit and Receive FIFOs can be cleared and reset independently of each other. The
status of the transmitter can be checked to see if it is empty, and if there is a character being transmitted. The status
of the receiver can also be checked, indicating if conditions such as parity error, framing error or break indication
have occurred. It also shows if an overrun error occurred (receive buffer full and another character arrives) and if
there is data held in the receive FIFO.
UART 0 signals CTS, RTS, TXD and RXD are alternate functions of pins DIO4, 5, 6 and 7 respectively and UART 1
signals CTS, RTS, TXD and RXD are alternate functions of pins DIO17, 18, 19 and 20 respectively. If CTS and RTS
are not required on the devices external pins, then they may be disabled. This allows the freed DIOs to be used for
other purposes.
Note: The automatic hardware flow control within the UART block negates RTS when the receive FIFO is about to
become full. This occurs when the UART has started receiving the last byte that it can accept. In some instances it
has been observed that remote devices that are transmitting data do not respond quickly enough to the de-asserted
RTS output and continue to transmit data. In these instances the data will be lost in a receive FIFO overflow, e.g. a
FTDI USB to serial cable.
13.1 Interrupts
Interrupt generation can be controlled for the UART block, and is divided into four categories:
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13.2 UART Application
The following example shows the UART connected to a 9-pin connector compatible with a PC. The software
developer kit uses such an interface as the debugger interface between the JN5139 and a PC. As the JN5139
device pins do not provide the RS232 line voltage a level shifter is used.
© NXP Laboratories UK 2010
Received Data Available: Is set when data in the Rx FIFO queue reaches a particular level (the trigger level can
be configured as 1, 4, 8 or 14) or if no character has been received for 4 character times.
Transmit FIFO Empty: set when the last character from the Tx FIFO is read and starts to be transmitted.
Receiver Line Status: set when one of the following occur (1) Parity Error - the character at the head of the
receive FIFO has been received with a parity error, (2) Overrun Error - the Rx FIFO is full and another character
has been received at the Receiver shift register, (3) Framing Error - the character at the head of the receive
FIFO does not have a valid stop bit and (4) Break Interrupt – occurs when the RxD line has been held low for an
entire character.
Modem Status: Generated when the CTS (Clear To Send) input control line changes.
JN5139
UART0
46
44
47
45
RTS
RXD
TXD
CTS
Figure 34 JN5139 Serial Communication Link
JN-DS-JN5139 1v9
RS232
Shifter
Level
PC COM Port
1
6
9
5
Pin
1
2
3
4
5
6
7
8
9
Signal
DSR
DTR
RTS
CTS
SG
CD
RD
TD
RI
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