IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 357

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Additional Information
Revision History
December 2010 Altera Corporation
November
2008
Date
Version
8.1
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Added new material on root port which is available for the hard IP implementation in
Stratix IV GX devices.
Changed to full support for Gen2 ×8 in the Stratix IV GX device.
Added discussion of dynamic reconfiguration of the transceiver for Stratix IV GX devices.
Refer to
Updated Resource Usage and Performance numbers for Quartus II 8.1 software
Added text explaining where TX I/Os are constrained. (Chapter 1)
Corrected Number of Address Pages in
Revised the
Assert_INTC, Assert_INTD, Deassert_INTB, Deassert_INTC and Deassert_INTD are not
generated by the core.
Clarified definition of rx_ack. It cannot be used to backpressure rx_data.
Corrected descriptions of cpl_err[4] and cpl_err[5] which were reversed. Added the
fact that the cpl_err signals are pulsed for 1 cycle.
Corrected 128-bit RX data layout in
Figure
Added explanation that for tx_cred port, completion header, posted header, non-
posted header and non-posted data fields, a value of 7 indicates 7 or more available
credits.
Added warning that in the Cyclone III designs using the external PHY must not use the dual-
purpose V
Revised
Corrected (reversed) positions of the SMI and EPLAST_ENA bits in
Added note that the RC slave module which is by default not instantiated in the
Testbench and Design Example
interface to a commercial BIOS.
Added definitions for test_out in hard IP implementation.
Removed description of Training error bit which is not supported in PCI Express
Specifications 1.1, 2.0 or 1.0a for endpoints.
5–19,
Table
Figure
REF
Table 9–2 on page
Figure
pins.
5–30.
14–6. For 8.1 txclk goes through a flip flop and is not inverted.
5–20, and
Figure
9–2. The following message types Assert_INTB,
must be instantiated to avoid deadline in designs that
Figure
Changes Made
5–21.
Table
5–10,
3–6.
Figure
5–11,
Figure
PCI Express Compiler User Guide
Table
5–12,
15–12.
Figure
Chapter 15,
5–13,
Info–5
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