IPR-PCI/T32 Altera, IPR-PCI/T32 Datasheet - Page 6

• Manufacturer Part Number: IPR-PCI/T32
• Description: IP CORE Renewal Of IP-PCI/T32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/T32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Compiler
6
Preliminary
Version
Table 2. PCI Compiler Revision History
4.0.0
3.2.0
3.1.0
3.0.0
April 2005
June 2004
April 2004
February 2004
Date
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Updated user guide of the PCI Compiler. Divided the user guide into two
sections. The first section contains the previous version of the user guide,
which describes the PCI Compiler with the MegaWizard flow. The second
section describes the PCI Compiler with the SOPC Builder flow, new feature
added in v4.0.0 of the PCI Compiler.
Provided an SOPC Builder ready PCI component.
PCI MegaCore function fixes
Corrected the problem when
during dual address cycle transactions if
the address phase in the single-cycle master read transaction.
Added support for the PCI Local Bus Specification, Revision 3.0
Added preliminary support for MAX II device family Added support for the PCI
Local Bus Specification, Revision 2.3 Concatenated the constraint files of all
the device densities and packages for a given device family to a single
constraint file Tcl script. For example, the pci310_q40sp1_cyclone_cf.tcl Tcl
script includes PCI constraints for all the PCI supported devices and
packages in the Cyclone family. Includes constraint files for all supported
device families and development boards Modified the installation directory
structure to include example Quartus II projects for all PCI MegaCore
functions in the /qexample directory PCI MegaCore function fixes.
Corrected the problem that had previously caused the PCI bus to behave
badly when a single cycle master write transaction, in which
asserted in the same clock cycle as
interface, resulted in the
Added preliminary support for Stratix II device family
Added OpenCore
Updated the pci_mt64 and pci_mt32 reference designs to support Stratix II,
Stratix, Stratix GX, and Cyclone devices
Made PCI MegaCore function fixes:
- Corrected the master's handling retry in the case where the local logic does
not assert
- Corrected the target read data output when the
previous target write transaction is overly extended to the current transaction.
- Fixed the problem where incorrect data was transferred to the local side
when
and the PCI MegaCore function also was performing a target write
transaction.
Added preliminary support for Cyclone II device family
lm_req32n
lm_rdyn
®
Plus evaluation feature
or
signal.
lm_req64n
framen
framen
Revision
signal on the PCI bus to stay low.
was asserted by the local master logic
lm_adr_ackn
and
lm_lastn
req64n
lt_rdyn
are not asserted properly
signal is asserted during
on the local side
Altera Corporation
signal from the
lm_rdyn
was