EVAL-ADUC7026QSZ Analog Devices Inc, EVAL-ADUC7026QSZ Datasheet - Page 14

• Manufacturer Part Number: EVAL-ADUC7026QSZ
• Description: Analog MCU Evaluation Board
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC7026QSZ

• Silicon Manufacturer: Analog Devices
• Core Architecture: ARM
• Core Sub-architecture: ARM7TDMI
• Silicon Core Number: ADuC7026
• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• Development Tool Type: Hardware / Software - Dev Kit (Dev Tool)
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7026
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADuC7019/20/21/22/24/25/26/27/28/29
Table 8. SPI Slave Mode Timing (Phsae Mode = 1)
Parameter
t
t
t
t
t
t
t
t
t
t
t
1
2
CS
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
SFS
t
t
UCLK
HCLK
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 57.
depends on the clock divider or CD bits in the PLLCON MMR. t
(POLARITY = 0)
(POLARITY = 1)
Description
CS to SCLOCK edge
SCLOCK low pulse width
SCLOCK high pulse width
Data output valid after SCLOCK edge
Data input setup time before SCLOCK edge
Data input hold time after SCLOCK edge
Data output fall time
Data output rise time
SCLOCK rise time
SCLOCK fall time
CS high after SCLOCK edge
SCLOCK
SCLOCK
MISO
MOSI
CS
1
t
CS
2
2
t
t
DSU
DAV
t
SH
Figure 8. SPI Slave Mode Timing (Phase Mode = 1)
MSB IN
HCLK
1
t
DHD
= t
t
MSB
1
SL
Rev. C | Page 14 of 96
UCLK
t
/2
DF
CD
; see Figure 57.
Min
(2 × t
1 × t
2 × t
0
t
UCLK
UCLK
DR
BITS 6 TO 1
HCLK
BITS 6 TO 1
) + (2 × t
UCLK
t
SR
)
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
5
5
5
5
LSB IN
t
SF
LSB
t
SFS
HCLK
HCLK
Max
25
12.5
12.5
12.5
12.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns