SC4519HEVB-1 Semtech, SC4519HEVB-1 Datasheet - Page 10

• Manufacturer Part Number: SC4519HEVB-1
• Description: EVALUATION BOARD
• Manufacturer: Semtech

Specifications of SC4519HEVB-1

• Silicon Manufacturer: Semtech
• Application Sub Type: Step Down Switching Regulator
• Kit Application Type: Power Management - Voltage Regulator
• Silicon Core Number: SC4519H
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The junction temperature of the SC4519H can be
further determined by:
Its value is a function of the IC package, the application
layout and the air cooling system.
The freewheeling diode also contributes a significant
portion of the total converter loss. This loss should be
minimized to increase the converter efficiency by using
Schottky diodes with low forward drop (V
Loop Compensation Design
The SC4519H has an internal error amplifier and requires
a compensation network to connect between the COMP
pin and GND pin as shown in Figure 3. The compensation
network includes C4, C5 and R3. R1 and R2 are used to
program the output voltage according to:
Assuming the power stage ESR (equivalent series
resistance) zero is an order of magnitude higher than
the closed loop bandwidth, which is typically one tenth of
the switching frequency, the power stage control to output
transfer function with the current loop closed (Ridley
model) for the SC4519H will be as follows:
Where:
R
C – Output capacitor.
The goal of the compensation design is to shape the loop
to have a high DC gain, high bandwidth, enough phase
margin, and high attenuation for high frequency noises.
Figure 3 gives a typical compensation network which
offers 2 poles and 1 zero to the power stage:
POWER MANAGEMENT
Application Information (Cont.)
L
2007 Semtech Corp.
JA
– Load and
is the thermal resistance from junction to ambient.
P
T
diode
J
G
V
T
VD
O
A
(s)
V
F
0
θ
8 .
JA
I
o
1
(1
1 (
P
5
total
R
D)
R
L
R
R
s
1
L
2
1
C
)
F
).
10
Figure 3. Compensation network provides 2 poles and
1 zero.
The compensation network gives the following
characteristics:
Where:
The loop gain will be given by:
Where:
One integrator is added at origin to increase the DC gain.
loop gain has –20dB/dec rate when it reaches 0dB line.
frequency switching noises. Figure 4 gives the asymptotic
diagrams of the power stage with current loop closed
and its loop gain.
T(s)
Z
P2
is used to cancel the power stage pole
is placed at half switching frequency to reject high
G
2
5
8
COMP
EN
IN
SYNC
(s)
G
COMP
G
SC4519H
COMP
VD
SW
FB
(s)
(s)
3
6
7
C5
4.25
ω
ω
1
P2
ω
ω
ω
1
s
Z
10
p1
R3
C4
1
(1
R
C
3
C
R
3
R
4
ω
4
3
R
C
ω
C
L
s
1
1
1
Z
L
4
s
P2
C
4
D2
C
C
C
4
5
R
5
C
)
L1
1
5
R
g
2
m
R
R2
R1
2
R
SC4519H
1
s
1
C
R
(1
www.semtech.com
2
R
P1
2
ω
s
Vout
P1
1
so that the
)
ω
(1
s
Z
ω
s
P2
)