CDB5541 Cirrus Logic Inc, CDB5541 Datasheet - Page 5

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CDB5541

Manufacturer Part Number
CDB5541
Description
Development Kit
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CDB5541

Silicon Manufacturer
Cirrus Logic
Application Sub Type
ADC
Kit Application Type
Data Converter
Silicon Core Number
CS5541
Features
RS-232 Serial Communication With PC, Chip Control And Data Capture, FFT Analysis
Kit Contents
Board
Rohs Compliant
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
ured to communicate via RS-232 at 19200 baud, no
parity, 8-bit data, and 1 stop bit. The baud rate can
be changed with software to go as fast as 38400
baud.
The microcontroller can be reset by depressing
pushbutton switch S1. On reset or upon power-up,
the LED’s on the board will count down, until only
LED4 remains lit. This LED is the POWER LED,
and informs the user that the board is powered on.
LED1, the BUSY LED, lights when the microcon-
troller is busy performing an operation. It is normal
for the LED to turn on and off, and is useful when
collecting large data sets.
1.2.3 Serial Interface
The CS5540/41 serial interface is SPI
CROWIRE
lines (CS, SDO, and SCLK) are connected to the
AVR microcontroller on the CDB5540/41.
1.2.4 Clock Source Options
The evaluation board provides three sources for the
master clock: the on-board crystal, the microcon-
troller, and an external clock signal.
1) The 32.768 kHz crystal oscillator can be chosen
by selecting the “Crystal Oscillator - 32.768 kHz”
option in the software. HDR2 on the evaluation
board should be set according to Table 3.
2) The microcontroller can be used to generate a
clock for the ADC. The microcontroller’s clock can
be chosen by selecting the “Microcontroller” op-
tion in the software. HDR2 on the evaluation board
should be set according to Table 3.
The clock frequency can be selected by changing
the “Oscillator Frequency” box in the software.
Note that the frequency options are limited by the
microcontroller’s counter/timer circuitry, which di-
DS503DB1
TM
compatible. The interface control
and MI-
vides the 3.6864 MHz clock by integer values to
produce the clock output.
3) An external clock can be provided by the user,
and connected to the XOSC post on J5. The “Exter-
nal Clock Source” option in the software should be
selected when using an external clock source, and
HDR2 on the evaluation board should be set ac-
cording to Table 3.
1.2.5 Headers, Jumpers, and DIP Switches
Table 1 describes the headers and DIP switches on
the evaluation board, with their appropriate default
settings.
Table 2 describes the various jumper settings for
HDR11 and HDR9, which select the voltage refer-
ence that is used.
HDR2 selects the MCLK source that is used. Jump-
er settings are depicted in Table 3.
DIP switch SW1 is used to control the AVR modes
and Table 4 illustrates the various modes it can be
set to. When testing the RS-232 link in the PC soft-
ware, the DIP switches should all be in the
CLOSED position.
Configurations other than those specified are not
recommended.
CDB5540 CDB5541
5

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