CDB43122 Cirrus Logic Inc, CDB43122 Datasheet - Page 4

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CDB43122

Manufacturer Part Number
CDB43122
Description
Development Kit
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CDB43122

Silicon Manufacturer
Cirrus Logic
Application Sub Type
DAC
Kit Application Type
Data Converter
Silicon Core Number
CS43122
Features
Supports PCM Audio & SACD Audio, Requires Only Digital Signal Source
Kit Contents
Evaluation Board
Rohs Compliant
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
7. OUTPUT FILTER
The output buffer/filter uses a balanced configura-
tion. The balanced output filter consist of the 301
ohm resistors and the 2200pf capacitor, and is de-
signed to cancel out the opposing multibit step pat-
tern in each analog output to create a very low out
of band noise spectrum. The op-amps provide out-
put buffering and are configured to provide a
+4.5db boost when the board switches into DSD
mode to compensate for the 4.5db gain loss of the
CS4397 in DSD mode. The balanced outputs are
AC coupled and are provided on board by XLR
type connectors.
8. POWER SUPPLIES
The CDB43122 comes supplied with an external
14 VAC Wall Mount power supply for conve-
nience in setup, and to make measurements easier
by eliminating ground loop problems between lab
power supplies and measurement equipment (Note:
the provided wall mount supply only operates at
110/120V and 50/60 Hz). The external 14 VAC
voltage supplied at J11 is rectified, filtered and reg-
ulated to produce +/-12 volts by regulators U13 and
U14. Separate voltage regulation is used for the
digital control circuitry (CS8414) and for the digi-
tal power section and analog section for the
CS43122 - CS4397. The digital power for the
CS43122 - CS4397 is user selectable by switch #9
on dip switch S2. The open position sets the voltage
regulator VREG2 to +5.0 volts, the closed position
sets the voltage regulator to +3.3 volts.
The CDB43122 evaluation board can also be pow-
ered by an external lab power supply by connecting
+12 vdc to the +12V (J8) binding post, -12 vdc to
12V
volts is allowed before reverse voltage protection
4
(J10), and ground to GND (J9). Up to +/- 13
-
diodes D3 and D4 will clamp the input voltage.
With JP5 connected, the +5V, VD and VA supplies
will be regulated from the supplied +12V. To pro-
vide VA and VD externally via the designated
binding posts, remove JP5 and lift pin 3 (bottom
right pin) on VREG1; +5V to the CS8414 will still
be provided by the on board regulator.
WARNING: refer to the CS43122 datasheet for
maximum allowable voltage levels. Operation out-
side this range can cause permanent damage to the
device.
9. GROUNDING AND POWER SUPPLY
For the user to be able to realize the high perfor-
mance capabilities of the CS43122 or CS4397, it is
recommended to pay careful attention to PC board
layout, grounding, and placement of the power sup-
ply and decoupling capacitors. It is recommended
when doing the PC board layout to use one ground
plane underneath the part for both the analog and
digital sections. Please review the attached PC
board photo plots for an example of the suggested
grounding method.
It is also recommended to pay careful attention to
the placement of the decoupling capacitors tied to
VREF (pin 28). This pin requires a very low im-
pedance path to ground at high frequencies as this
pin draws high frequency current pulses at 6 MHz.
It is important to place the .01 uf capacitor and
100 uf capacitor right next to the pin. Keep the con-
necting trace as short as possible. High perfor-
mance capacitors such as NPO for the .01 uf and a
low ESR electrolytic or tantalum for the 100 uf are
recommended. Low frequency distortion (0-40Hz)
performance can also be improved by increasing
the FILT+ (pin 27) capacitance value up to 470uf.
DECOUPLING
CDB43122
DS526DB1

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