ADIS16220/PCBZ Analog Devices Inc, ADIS16220/PCBZ Datasheet - Page 11

• Manufacturer Part Number: ADIS16220/PCBZ
• Description: Vibration Sensor Evaluation Board
• Manufacturer: Analog Devices Inc
• Series: iSensor™r

Specifications of ADIS16220/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Vibration Sensor
• Kit Application Type: Sensing - Motion / Vibration / Shock
• Silicon Core Number: ADIS16220
• Kit Contents: Board
• Sensor Type: Vibration, Accelerometer
• Sensing Range: ±70g
• Interface: SPI Serial
• Sensitivity: 19.073mg/LSB
• Voltage - Supply: 3.15 V ~ 3.6 V
• Embedded: No
• Utilized Ic / Part: ADIS16220
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DATA COLLECTION
The ADIS16220 samples and stores acceleration (vibration) and
analog input signal data using capture events. A capture event
involves several sampling/processing operations, as shown in
Figure 14. First, the ADIS16220 produces and stores 1024
samples of acceleration and analog input channel data into
the capture buffers. Second, the capture event takes a 5.12 ms
record of power supply measurements at a sample rate of
50 kHz and loads the average of this record into the CAPT_
SUPPLY register. Third, the capture event takes 64 samples of
internal temperature data over a period of 1.7 ms and loads the
average of this record into CAPT_TEMP.
READING DATA FROM THE CAPTURE BUFFER
When a capture is complete, the first data samples load into the
CAPT_BUFx registers and 0x0000 loads into the index pointer
(CAPT_PNTR). The index pointer determines which data sam-
ples load into the CAPT_BUFx registers. For example, writing
0x0138 to the CAPT_PNTR register (DIN = 0x9A38, DIN =
0x9B01) causes the 313
into the CAPT_BUFx registers.
Table 9. CAPT_PNTR Bits Descriptions
Bit
[15:10]
[9:0]
The index pointer automatically increments with a CAPT_BUFA,
CAPT_BUF1, or CAPT_BUF2 read command, which causes
the next set of capture data to load into each capture buffer
register.
Output Data Format
Table 10 offers a summary of the data format used by each
output registers. Table 11, Table 12, Table 13, and Table 14
provide example output coding for each register.
INTERNAL SAMPLING SYSTEM FILLS THE CAPTURE BUFFER
AND OUTPUT REGISTERS
CAPT_PNTR
CAPT_BUF1 (AIN1) and CAPT_BUF2 (AIN2) Use Similar Structures
Figure 14. Acceleration Capture Buffer Structure and Operation;
1023
0
Description (Default = 0x0000)
Reserved
Data bits
CAPTURE
BUFFER
AIN2
th
DATA IN BUFFERS LOAD INTO
sample in the buffer memory to load
USER OUTPUT REGISTERS
CAPTURE
BUFFER
AIN1
ACCELER-
CAPTURE
OMETER
BUFFER
CAPTURE BUFFER
TRIPLE-CHANNEL
1024 SAMPLES
16-BIT DATA
CAPT_SUPPLY
CAPT_BUF2
CAPT_BUF1
CAPT_BUFA
CAPT_TEMP
EACH
Rev. 0 | Page 11 of 20
Table 10. Capture Output Register Formats
Register
CAPT_SUPPLY
CAPT_TEMP
CAPT_BUFA,
CAPT_PEAKA
CAPT_BUF1,
CAPT_BUF2,
CAPT_PEAK1,
CAPT_PEAK2
1
Table 11. CAPT_BUFA
Acceleration (g)
+70
+0.019073
0
−0.019073
−70
1
Table 12. CAPT_BUF1
Level (mV)
VDD/2+1000
VDD/2+0.305
VDD/2
VDD/2−0.305
VDD/2−1000
1
2
Table 13. CAPT_SUPPLY Data Format Examples
Supply Level (V)
3.6
3.3 + 0.0012207
3.3
3.3 – 0.0012207
3.15
Table 14. CAPT_TEMP Data Format Examples
Temperature (°C)
+125
+25.47
+25
+24.53
−40
12-bit data formats are LSB justified. Upper four bits are not used in these cases.
This table also applies to the CAPT_PEAKA register.
This table also applies to CAPT_BUF2, CAPT_PEAK1, and CAPT_PEAK2
registers.
This applies for MSC_CTRL = 0x0003. When MSC_CTRL = 0x0000, substitute
3300 mV for VDD.
2
Format
12-bit binary, 0 V = 0 LSB,
1.2207 mV/LSB
12-bit binary, +25°C = 1278 LSB,
−0.47°C/LSB
16-bit twos complement
19.073 mg/LSB
16-bit twos complement
305.18 μV/LSB
LSB
+3277
+1
0
−1
−3277
LSB
+3670
+1
0
−1
−3670
LSB
2949
2704
2703
2702
2580
1
LSB
1065
1277
1278
1279
1416
1
1
Data Format Examples
Data Format Examples
Hex
0x0CCD
0x0001
0x0000
0xFFFF
0xF333
Hex
0x0E56
0x0001
0x0000
0xFFFF
0xF1AA
Hex
0x429
0x4FD
0x4FE
0x4FF
0x588
Hex
0xB85
0xA90
0xA8F
0xA8E
0xA14
Output (Binary)
0000 1100 1100 1101
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 0011 0011 0011
Output (Binary)
0000 1110 0101 0111
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 0001 1010 1010
Binary Output
0100 0100 1001
0100 1111 1101
0100 1111 1110
0100 1111 1111
0101 1000 1000
Binary Output
1011 1000 0101
1010 1001 0000
1010 1000 1111
1010 1000 1110
1010 0001 0100
ADIS16220
Reference
Table 13
Table 14
Table 11
Table 12