AD9649-80EBZ Analog Devices Inc, AD9649-80EBZ Datasheet
AD9649-80EBZ
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AD9649-80EBZ Summary of contents
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... DIVIDE CLK+ CLK– Figure 1. PRODUCT HIGHLIGHTS 1. The AD9649 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1 3.3 V logic families. 2. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use ...
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... Timing Specifications .................................................................. 8 Absolute Maximum Ratings ............................................................ 9 Thermal Characteristics .............................................................. 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 11 AD9649-80 .................................................................................. 11 AD9649-65 .................................................................................. 13 AD9649-40 .................................................................................. 14 AD9649-20 .................................................................................. 15 Equivalent Circuits ......................................................................... 16 Theory of Operation ...................................................................... 17 Analog Input Considerations .................................................... 17 REVISION HISTORY 10/09—Revision 0: Initial Version Voltage Reference ....................................................................... 19 Clock Input Considerations ...................................................... 20 ...
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... GENERAL DESCRIPTION The AD9649 is a monolithic, single channel 1.8 V supply, 14-bit, 20/40/65/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and an on-chip volt- age reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range ...
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... Rev Page AD9649-80 Typ Max Min Typ Max 14 Guaranteed +0.05 +0.50 −0.40 +0.05 +0.50 −1.5 −1.5 +0.55 ±0.65 ±0.3 ±0.35 ±1.30 ±1.75 ± ...
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... Full −90 25°C −100 Full 25°C −95 25°C 90 25°C 700 Rev Page AD9649 AD9649-65 AD9649-80 Typ Max Min Typ Max 74.5 74.3 74.3 74.1 73.7 73.6 72.7 71.5 71.5 74.4 74.1 74.2 74.0 73.6 73 ...
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... DRVDD = 1.8 V High Level Output Voltage ( μ 0 Low Level Output Voltage ( 1 μ Internal 30 kΩ pull-down. 2 Internal 30 kΩ pull-up. AD9649-20/AD9649-40/AD9649-65/AD9649-80 Temp Min Full Full 0.2 Full GND − 0.3 Full −10 Full −10 Full 8 Full 1 Full 1.2 Full 0 Full −50 Full − ...
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... PD Figure 2. CMOS Output Data Timing Rev Page AD9649-65 AD9649-80 Min Typ Max Min Typ 260 15.38 12.5 7.69 6.25 1.0 1.0 0.1 0 0.1 0 350 350 300 260 – – – 4 AD9649 Max Unit 320 MHz 80 MSPS rms Cycles μs ns Cycles ...
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... AD9649 TIMING SPECIFICATIONS Table 5. Parameter Conditions SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK DS t Hold time between the data and the rising edge of SCLK DH t Period of the SCLK CLK t Setup time between CSB and SCLK ...
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... ESD CAUTION Rev Page Airflow Velocity θ θ θ (m/sec 37.1 3.1 20.7 1.0 32.4 2.5 29.1 is specified for a 4-layer PCB with a solid ground addition, metal in direct contact with the AD9649 Ψ 1,2 Unit JT 0.3 °C/W 0.5 °C/W 0.8 °C/W ...
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... VIN−, VIN+ ADC Analog Inputs. CLK AVDD PIN 1 CLK– MODE/OR INDICATOR AVDD 3 22 DCO CSB 4 AD9649 21 D13 (MSB) SCLK/DFS 5 20 D12 TOP VIEW 6 19 D11 (Not to Scale) D0 (LSB D10 PLANE OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND MAXIMIZE THE HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. ...
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... Figure 6. AD9649-80 Two-Tone FFT with f = 30.5 MHz and f IN1 9.7 MHz 70.3 MHz IN 2F1 – F2 2F2 – 32.5 MHz Figure 9. AD9649-80 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) IN2 Rev Page 80MSPS 30.5MHz @ –1dBFS –15 SNR = 73.2dB (74.2dBFS) SFDR = 93.6dBc –30 –45 –60 –75 – –105 –120 ...
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... Figure 10. AD9649-80 SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale 120 SFDR (dBc) 100 SNR (dBFS SAMPLE RATE (MSPS) Figure 11. AD9649-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 2048 4096 6144 8192 ...
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... SNR = 73.3dB (74.3dBFS) SFDR = 99.3dBc –30 –45 –60 –75 –90 2 –105 6 4 –120 FREQUENCY (MHz) Figure 18. AD9649-65 Single-Tone FFT with 9.7 MHz Figure 19.AD9649-65 SNR/SFDR vs. Input Amplitude (AIN) with 70.3 MHz 30.5 MHz IN Rev Page 120 SFDRFS 100 80 SNRFS 60 SFDR 40 ...
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... FREQUENCY (MHz) Figure 22. AD9649-40 Single-Tone FFT with f 120 100 –90 = 9.7 MHz Figure 23. AD9649-40 SNR/SFDR vs. Input Amplitude (AIN) with 30.5 MHz IN Rev Page AD9649 SFDRFS SNRFS SFDR SNR –80 –60 –40 –20 INPUT AMPLITUDE (dBFS 9.7 MHz IN ...
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... FREQUENCY (MHz) Figure 25. AD9649-20 Single-Tone FFT with f 120 100 –100 = 9.7 MHz Figure 26. AD9649-20 SNR/SFDR vs. Input Amplitude (AIN) with 30.5 MHz IN Rev Page SFDR (dBFS) SNR (dBFS) SFDR (dBc) SNR (dBc) –90 –80 –70 – ...
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... AD9649 EQUIVALENT CIRCUITS AVDD VIN± Figure 27. Equivalent Analog Input Circuit AVDD VREF 7.5kΩ Figure 28. Equivalent VREF Circuit AVDD 375Ω SENSE Figure 29. Equivalent SENSE Circuit 5Ω CLK+ 15kΩ 15kΩ 5Ω CLK– Figure 30. Equivalent Clock Input Circuit 375Ω ...
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... Converters” (Volume 39, April 2005) for more information. In general, the precise values depend on the application. Input Common Mode The analog inputs of the AD9649 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide an external dc bias. Setting the device so that VCM = AVDD/2 ...
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... ADA4938-2 provide excellent performance and a flexible interface to the ADC. The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9649 (see Figure 38), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. 200Ω ...
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... SELECT LOGIC SENSE Figure 43. Internal Reference Configuration If the internal reference of the AD9649 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 44 shows how the internal reference voltage is affected by loading. External Reference Operation ...
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... Jitter Considerations section. Figure 47 and Figure 48 show two preferred methods for clock- ing the AD9649. The CLK inputs support up to 4× the rated sample rate when using the internal clock divider feature. A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF transformer balun. ® ...
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... Figure 53. SNR vs. Input Frequency and Jitter The clock input should be treated as an analog signal in cases in which aperture jitter may affect the dynamic range of the AD9649. To avoid modulating the clock signal with digital noise, keep power supplies for clock drivers separate from the ADC output driver supplies ...
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... At clock rates below 3 MSPS, dynamic performance may degrade. Data Clock Output (DCO) The AD9649 provides a data clock output (DCO) signal that is intended for capturing the data in an external register. The CMOS data outputs are valid on the rising edge of DCO, unless the DCO clock polarity has been changed via the SPI ...
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... AD9649. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9649 signal path. Perform the BIST test after a reset to ensure that the part known state. During the BIST test, data from an internal pseudorandom noise (PN) source is driven through the digital datapath of both channels, starting at the ADC block output ...
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... AD9649 SERIAL PORT INTERFACE (SPI) The AD9649 SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port ...
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... The pins described in Table 13 constitute the physical interface between the programming device of the user and the serial port of the AD9649. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...
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... SPI map (for example, Address 0x13) and should not be written. DEFAULT VALUES After the AD9649 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 16). ...
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... Offset adjust in LSBs from +127 to −128 (twos complement format) Bit 5 Bit 4 Bit 3 Bit 2 Soft 1 1 Soft reset reset 8-bit chip ID, Bits[7:0] AD9649 = 0x6F Speed grade ID, Bits[6:4] 20 MSPS = 000 40 MSPS = 001 65 MSPS = 010 80 MSPS = 011 Open Open Open Open Open Open Open ...
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... AD9649 Addr. (MSB) (Hex) Register Name Bit 7 Bit 6 0x14 Output mode 00 = 3.3 V CMOS 10 = 1.8 V CMOS 0x15 Output adjust 3.3 V DCO drive strength stripe (default stripes stripes stripes 0x16 Output phase DCO Open output polarity 0 = normal 1 = inv 0x17 Output delay Enable Open ...
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... MSPS, it may be preferable to set this bit high to supersede the GCLK detector. Bit 0—Disable SDIO Pull-Down Bit 0 can be set high to disable the internal 30 kΩ pull-down on the SDIO pin, which can be used to limit the loading when many devices are connected to the SPI bus. Rev Page AD9649 ...
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... Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com. Encode Clock For optimum dynamic performance, use a low jitter encode clock source with a 50% duty cycle (±5%) to clock the AD9649. VCM The VCM pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 39. ...
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... AD9649BCPZRL7-40 –40°C to +85° AD9649BCPZ-20 –40°C to +85°C AD9649BCPZRL7- –40°C to +85°C 1 AD9649-80EBZ AD9649-65EBZ 1 1 AD9649-40EBZ 1 AD9649-20EBZ RoHS Compliant Part. 2 The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND. ...
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... AD9649 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08539-0-10/09(0) Rev Page ...