AD9255-80EBZ Analog Devices Inc, AD9255-80EBZ Datasheet - Page 31

• Manufacturer Part Number: AD9255-80EBZ
• Description: A/D Converter Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9255-80EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9255
• Kit Contents: Board
• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 80M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 239mW @ 80MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9255
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Treat the clock input as an analog signal in cases in which
aperture jitter may affect the dynamic range of the AD9255. To
avoid modulating the clock signal with digital noise, separate
power supplies for clock drivers from the ADC output driver
supplies. Low jitter, crystal controlled oscillators make the best
clock sources. If the clock is generated from another type of source
(by gating, dividing, or another method), the output clock should
be retimed by the original clock at the last step.
Refer to AN-501 Application Note, Aperture Uncertainty and ADC
System Performance, and AN-756 Application Note, Sampled
Systems and the Effects of Clock Phase Noise and Jitter (see
www.analog.com) for more information about jitter performance
as it relates to ADCs.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 81, the power dissipated by the AD9255 is
proportional to its sample rate. In CMOS output mode, the digital
power dissipation is determined primarily by the strength of the
digital drivers and the load on each output bit.
The maximum DRVDD current (IDRVDD) can be approximately
calculated as
where N is the number of output bits (14 output bits plus
one DCO).
This maximum current occurs when every output bit switches on
every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of f
by the average number of output bits switching, which is deter-
mined by the sample rate and the characteristics of the analog
input signal.
Reducing the capacitive load presented to the output drivers
can minimize digital power consumption. The data in Figure 81,
Figure 82, and Figure 83 was taken using a 70 MHz analog input
signal, with a 5 pF load on each output driver.
IDRVDD = VDRVDD × C
80
75
70
65
60
55
50
1
MEASURED
CLK
Figure 80. SNR vs. Input Frequency and Jitter
/2. In practice, the DRVDD current is established
INPUT FREQUENCY (MHz)
10
LOAD
× f
CLK
100
× N
0.05ps
0.20ps
0.50ps
1.00ps
1.50ps
1k
Rev. A | Page 31 of 44
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD9255 is placed in power-down
mode. In this state, the ADC typically dissipates 0.05 mW.
During power-down, the output drivers are placed in a high
impedance state; asserting the PDWN pin low returns the
AD9255 to its normal operating mode.
0.5
0.4
0.3
0.2
0.1
0.5
0.4
0.3
0.2
0.1
0.5
0.4
0.3
0.2
0.1
0
0
0
25
25
25
Figure 81. AD9255-125 Power and Current vs. Sample Rate
Figure 82. AD9255-105 Power and Current vs. Sample Rate
Figure 83. AD9255-80 Power and Current vs. Sample Rate
35
35
45
50
ENCODE FREQUENCY (MSPS)
CLOCK FREQUENCY (MSPS)
CLOCK FREQUENCY (MSPS)
IDRVDD
POWER
TOTAL
IAVDD
45
55
IDRVDD
POWER
TOTAL
IAVDD
POWER
IDRVDD
65
TOTAL
IAVDD
75
55
75
65
100
85
95
75
AD9255
105
125
0.15
0.12
0.09
0.06
0.03
0
0.20
0.16
0.12
0.08
0.04
0
0.20
0.16
0.12
0.08
0.04
0